void pirq_assign_irqs(const unsigned char pIntAtoD[4])
{
	device_t pdev;

	pdev = dev_find_device(PCI_VENDOR_ID_AMD,
			       PCI_DEVICE_ID_AMD_CS5536_ISA, 0);

	if (pdev) {
		pci_write_config16(pdev, 0x5c, (pIntAtoD[3] << 12
			| pIntAtoD[2] << 8 | pIntAtoD[1] << 4 | pIntAtoD[0]));
	}
}

void set_pcie_reset()
{
	u16 word;
	device_t sm_dev;
	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));

	word = pci_read_config16(sm_dev, 0xA8);
	word &= ~((1 << 0) | (1 << 2));	/* Set Gpio6,4 as output */
	word &= ~((1 << 8) | (1 << 10));
	pci_write_config16(sm_dev, 0xA8, word);
}

static void pch_enable_lpc(void)
{
	/* Parrot EC Decode Range Port60/64, Port62/66 */
	/* Enable EC, PS/2 Keyboard/Mouse */
	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);

	/* Map EC_IO decode to the LPC bus */
	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (EC_IO & ~3) | 0x00040001);

	/* Map EC registers 68/6C decode to the LPC bus */
	pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001);
}

static void ich7_enable_lpc(void)
{
	int lpt_en = 0;
	if (read_option(lpt, 0) != 0) {
		lpt_en = 1 << 2; /* enable LPT */
	}
	/* Enable Serial IRQ */
	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
	/* Set COM1/COM2 decode range */
	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
	/* Enable COM1/COM2/KBD/SuperIO1+2 */
	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en);
	/* Enable HWM at 0xa00 */
	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
	/* COM3 decode */
	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
	/* COM4 decode */
	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
	/* io 0x300 decode */
	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
}

void pch_enable_lpc(void)
{
	/*
	 * Enable:
	 *  EC Decode Range PortA30/A20
	 *  SuperIO Port2E/2F
	 *  PS/2 Keyboard/Mouse Port60/64
	 *  FDD Port3F0h-3F5h and Port3F7h
	 */
	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
			CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);

	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);

	pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);

	/* Initialize SuperIO */
	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	it8728f_b75md3h_disable_reboot(SUPERIO_GPIO);
}

static void ide_init(struct device *dev)
{
	u16 reg16;
	config_t *conf = dev->chip_info;

	reg16 = pci_read_config16(dev, IDE_TIM_PRI);
	reg16 &= ~IDE_DECODE_ENABLE;
	if (!conf || conf->ide0_enable)
		reg16 |= IDE_DECODE_ENABLE;
	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
	       conf->ide0_enable ? "on" : "off");
	pci_write_config16(dev, IDE_TIM_PRI, reg16);

	reg16 = pci_read_config16(dev, IDE_TIM_SEC);
	reg16 &= ~IDE_DECODE_ENABLE;
	if (!conf || conf->ide1_enable)
		reg16 |= IDE_DECODE_ENABLE;
	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
	       conf->ide0_enable ? "on" : "off");
	pci_write_config16(dev, IDE_TIM_SEC, reg16);
}

/*
 * Enables several BARs and devices which are needed for memory init
 * - MCH_BASE_ADDR is needed in order to talk to the memory controller
 * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded)
 *   Once raminit is done, we can safely let the allocator re-assign them
 * - HPET is enabled because FSP wants to store a pointer to global data in the
 *   HPET comparator register
 */
static void soc_early_romstage_init(void)
{
	device_t pmc = PMC_DEV;

	/* Set MCH base address and enable bit */
	pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1);

	/* Set PMC base addresses and enable decoding. */
	pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
	pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0);	/* 64-bit BAR */
	pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
	pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0);	/* 64-bit BAR */
	pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
	pci_write_config16(pmc, PCI_COMMAND,
				PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
				PCI_COMMAND_MASTER);

	/* Enable decoding for HPET. Needed for FSP global pointer storage */
	pci_write_config8(P2SB_DEV, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
						P2SB_HPTC_ADDRESS_ENABLE);
}

static void sata_init(struct device *dev)
{
	u32 reg32;
	u16 reg16;
	u32 abar;

	/* Get the chip configuration */
	config_t *config = dev->chip_info;

	printk(BIOS_DEBUG, "SATA: Initializing...\n");

	if (config == NULL) {
		printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
		return;
	}

	/* SATA configuration is handled by the FSP */

	/* Enable BARs */
	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER |
						     PCI_COMMAND_MEMORY |
						     PCI_COMMAND_IO);

	printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");

	/* Set the controller mode */
	reg16 = pci_read_config16(dev, SATA_MAP);
	reg16 &= ~(3 << 6);
	reg16 |= SATA_MAP_AHCI;
	pci_write_config16(dev, SATA_MAP, reg16);

	/* Initialize AHCI memory-mapped space */
	abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
	printk(BIOS_DEBUG, "ABAR: %08X\n", abar);

	/* Enable AHCI Mode */
	reg32 = read32((void *)(abar + 0x04));
	reg32 |= (1 << 31);
	write32((void *)(abar + 0x04), reg32);
}

/**
 * Send the specified RAM command to all DIMMs.
 *
 * @param command The RAM command to send to the DIMM(s).
 */
static void do_ram_command(u32 command)
{
	int i, caslatency;
	u8 dimm_start, dimm_end;
	u16 reg16;
	void *addr;
	u32 addr_offset;

	/* Configure the RAM command. */
	reg16 = pci_read_config16(NB, SDRAMC);
	reg16 &= 0xff1f;		/* Clear bits 7-5. */
	reg16 |= (u16) (command << 5);	/* Write command into bits 7-5. */
	pci_write_config16(NB, SDRAMC, reg16);

	/*
	 * RAM_COMMAND_NORMAL affects only the memory controller and
	 * doesn't need to be "sent" to the DIMMs.
	 */
	if (command == RAM_COMMAND_NORMAL)
		return;

	/* Send the RAM command to each row of memory. */
	dimm_start = 0;
	for (i = 0; i < (DIMM_SOCKETS * 2); i++) {
		addr_offset = 0;
		caslatency = 3; /* TODO: Dynamically get CAS latency later. */
		if (command == RAM_COMMAND_MRS) {
			/*
			 * MAA[12:11,9:0] must be inverted when sent to DIMM
			 * 2 or 3 (no inversion if sent to DIMM 0 or 1).
			 */
			if ((i >= 0 && i <= 3) && caslatency == 3)
				addr_offset = 0x1d0;
			if ((i >= 4 && i <= 7) && caslatency == 3)
				addr_offset = 0x1e28;
			if ((i >= 0 && i <= 3) && caslatency == 2)
				addr_offset = 0x150;
			if ((i >= 4 && i <= 7) && caslatency == 2)
				addr_offset = 0x1ea8;
		}

		dimm_end = pci_read_config8(NB, DRB + i);

		addr = (void *)((dimm_start * 8 * 1024 * 1024) + addr_offset);
		if (dimm_end > dimm_start) {
			read32(addr);
		}

		/* Set the start of the next DIMM. */
		dimm_start = dimm_end;
	}
}

static void poulsbo_setup_Stage2Regs(void)
{
	u16 reg16;

	printk(BIOS_DEBUG, "Reserved");
	reg16 = pci_read_config16(PCI_DEV(0, 0x2, 0), 0x62);
	pci_write_config16(PCI_DEV(0, 0x2, 0), 0x62, (reg16 | 0x3));
	/* Slot capabilities */
	pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500);
	pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500);
	/* FIXME: CPU ID identification */
	printk(BIOS_DEBUG, " done.\n");
}

void variant_mainboard_final(void)
{
	struct device *dev;
	uint16_t cmd = 0;

	/* Set Master Enable for on-board PCI device. */
	dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
	if (dev) {
		cmd = pci_read_config16(dev, PCI_COMMAND);
		cmd |= PCI_COMMAND_MASTER;
		pci_write_config16(dev, PCI_COMMAND, cmd);
	}
}

static void memctrl_init(device_t dev)
{
/*
  set VGA in uma_ram_setting.c, not in this function.
*/
#if 0
	pci_write_config8(dev, 0x85, 0x20);
	pci_write_config8(dev, 0x86, 0x2d);

	/* Set up VGA timers */
	pci_write_config8(dev, 0xa2, 0x44);

	/* Enable VGA with a 32mb framebuffer */
	pci_write_config16(dev, 0xa0, 0xd000);

	pci_write_config16(dev, 0xa4, 0x0010);

	//b0: 60 aa aa 5a 0f 00 00 00 08
	pci_write_config16(dev, 0xb0, 0xaa00);
	pci_write_config8(dev, 0xb8, 0x08);
#endif
}

void pch_enable_lpc(void)
{
	/* EC Decode Range Port60/64 and Port62/66 */
	/* Enable EC and PS/2 Keyboard/Mouse*/
	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);

	/* EC Decode Range Port68/6C */
	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001);

	/* EC Decode Range Port 380-387 */
	pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001);

}

static void pci_init(struct device *dev)
{
	u32 dword;
	device_t pci_domain_dev;
	struct resource *mem, *pref;

	dword = pci_read_config32(dev, 0x04);
	dword |= (1 << 8);	/* System error enable */
	dword |= (1 << 30);	/* Clear possible errors */
	pci_write_config32(dev, 0x04, dword);

#if 0
	word = pci_read_config16(dev, 0x48);
	word |= (1 << 0);	/* MRL2MRM */
	word |= (1 << 2);	/* MR2MRM */
	pci_write_config16(dev, 0x48, word);
#endif

#if 1
	dword = pci_read_config32(dev, 0x4c);
	dword |= 0x00440000;	/* TABORT_SER_ENABLE Park Last Enable. */
	pci_write_config32(dev, 0x4c, dword);
#endif

	pci_domain_dev = dev->bus->dev;
	while (pci_domain_dev) {
		if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
			break;
		pci_domain_dev = pci_domain_dev->bus->dev;
	}

	if (!pci_domain_dev)
		return;		/* Impossible */

	pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
	mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));

	if (!mem)
		return;		/* Impossible */

	if (!pref || pref->base > mem->base) {
		dword = mem->base & (0xffff0000UL);
		printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
	} else {
		dword = pref->base & (0xffff0000UL);
		printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
	}

	printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
	pci_write_config32(dev, 0x50, dword);	/* TOM */
}

static void usb_i_init(struct device *dev)
{
#if CONFIG_EPIA_VT8237R_INIT
	u8 reg8;

	printk(BIOS_DEBUG, "Entering %s\n", __func__);

	reg8 = pci_read_config8(dev, 0x04);

	printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8);

	reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_write_config8(dev, 0x04, reg8);

	printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8);

	/* Set Cache Line Size and Latency Timer */
	pci_write_config8(dev, 0x0c, 0x08);
	pci_write_config8(dev, 0x0d, 0x20);

	/* Enable Sub Device ID Back Door and set Generic */
	reg8 = pci_read_config8(dev, 0x42);
	reg8 |= 0x10;
	pci_write_config8(dev, 0x42, reg8);
	pci_write_config16(dev, 0x2e, 0xAA07);
	reg8 &= ~0x10;
	pci_write_config8(dev, 0x42, reg8);


	pci_write_config8(dev, 0x41, 0x12);

	pci_write_config8(dev, 0x49, 0x0B);

	/* Clear PCI Status */
	pci_write_config16(dev, 0x06, 0x7A10);
#endif
	return;
}

static void pci_init(struct device *dev)
{
	u16 reg16;
	u8 reg8;

	printk(BIOS_DEBUG, "PCI init.\n");
	/* Enable Bus Master */
	reg16 = pci_read_config16(dev, PCI_COMMAND);
	reg16 |= PCI_COMMAND_MASTER;
	pci_write_config16(dev, PCI_COMMAND, reg16);

	/* This device has no interrupt */
	pci_write_config8(dev, INTR, 0xff);

	/* disable parity error response and SERR */
	reg16 = pci_read_config16(dev, BCTRL);
	reg16 &= ~(1 << 0);
	reg16 &= ~(1 << 1);
	pci_write_config16(dev, BCTRL, reg16);

	/* Master Latency Count must be set to 0x04! */
	reg8 = pci_read_config8(dev, SMLT);
	reg8 &= 0x07;
	reg8 |= (0x04 << 3);
	pci_write_config8(dev, SMLT, reg8);

	/* Will this improve throughput of bus masters? */
	pci_write_config8(dev, PCI_MIN_GNT, 0x06);

	/* Clear errors in status registers */
	reg16 = pci_read_config16(dev, PSTS);
	//reg16 |= 0xf900;
	pci_write_config16(dev, PSTS, reg16);

	reg16 = pci_read_config16(dev, SECSTS);
	// reg16 |= 0xf900;
	pci_write_config16(dev, SECSTS, reg16);
}

static void pci_init(struct device *dev)
{
	u16 reg16;
	u8 reg8;

	/* This device has no interrupt */
	pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);

	/* Master Latency Count must be set to 0x04! */
	reg8 = pci_read_config8(dev, D30F0_SMLT);
	reg8 &= 0x07;
	reg8 |= (0x04 << 3);
	pci_write_config8(dev, D30F0_SMLT, reg8);

	/* Clear errors in status registers */
	reg16 = pci_read_config16(dev, PCI_STATUS);
	//reg16 |= 0xf900;
	pci_write_config16(dev, PCI_STATUS, reg16);

	reg16 = pci_read_config16(dev, PCI_SEC_STATUS);
	// reg16 |= 0xf900;
	pci_write_config16(dev, PCI_SEC_STATUS, reg16);
}

static void lpc_init(struct device *dev)
{
	printk(BIOS_DEBUG, "i82801gx: lpc_init\n");

	/* Set the value for PCI command register. */
	pci_write_config16(dev, PCI_COMMAND, 0x000f);

	/* IO APIC initialization. */
	i82801gx_enable_ioapic(dev);

	i82801gx_enable_serial_irqs(dev);

	/* Setup the PIRQ. */
	i82801gx_pirq_init(dev);

	/* Setup power options. */
	i82801gx_power_options(dev);

	/* Configure Cx state registers */
	i82801gx_configure_cstates(dev);

	/* Set the state of the GPIO lines. */
	//gpio_init(dev);

	/* Initialize the real time clock. */
	i82801gx_rtc_init(dev);

	/* Initialize ISA DMA. */
	isa_dma_init();

	/* Initialize the High Precision Event Timers, if present. */
	enable_hpet();

	/* Initialize Clock Gating */
	enable_clock_gating();

	setup_i8259();

	/* The OS should do this? */
	/* Interrupt 9 should be level triggered (SCI) */
	i8259_configure_irq_trigger(9, 1);

#if CONFIG_HAVE_SMI_HANDLER
	i82801gx_lock_smm(dev);
#endif

	i82801gx_spi_init();

	i82801gx_fixups(dev);
}

static void lpc_init(struct device *dev)
{
	printk(BIOS_DEBUG, "pch: lpc_init\n");

	/* Set the value for PCI command register. */
	pci_write_config16(dev, PCI_COMMAND, 0x000f);

	/* IO APIC initialization. */
	pch_enable_apic(dev);

	pch_enable_serial_irqs(dev);

	/* Setup the PIRQ. */
	pch_pirq_init(dev);

	/* Setup power options. */
	pch_power_options(dev);

	/* Initialize power management */
	switch (pch_silicon_type()) {
	case PCH_TYPE_CC: /* CaveCreek */
		break;
	default:
		printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
	}

	/* Set the state of the GPIO lines. */
	//gpio_init(dev);

	/* Initialize the real time clock. */
	pch_rtc_init(dev);

	/* Initialize ISA DMA. */
	isa_dma_init();

	/* Initialize the High Precision Event Timers, if present. */
	enable_hpet();

	setup_i8259();

	/* The OS should do this? */
	/* Interrupt 9 should be level triggered (SCI) */
	i8259_configure_irq_trigger(9, 1);

	pch_disable_smm_only_flashing(dev);

	pch_set_acpi_mode();

	pch_fixups(dev);
}

/**
 * Route all DMA channels to either PCI or LPC.
 *
 * @param dev TODO
 * @param mask Identifies whether each channel should be used for PCI DMA
 *             (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
 *             Channel 4 is not used (reserved).
 */
static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
{
    uint16_t dmaConfig;
    int channelIndex;

    dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
    dmaConfig &= 0x300;				// Preserve reserved bits
    for(channelIndex = 0; channelIndex < 8; channelIndex++) {
    	if (channelIndex == 4)
        	continue;		// Register doesn't support channel 4
        dmaConfig |= ((mask & (1 << channelIndex))? 3:1) << (channelIndex*2);
    }
    pci_write_config16(dev, PCI_DMA_CFG, dmaConfig);
}