void __init ixp2000_pci_init(void *sysdata)
{
	external_fault = ixp2000_pci_abort_handler;
	
	DBG("PCI: set upper mem io bits\n");
	*IXP2000_PCI_ADDR_EXT = 0x0;  

	if (npu_is_master()) {/* master NPU */
		pci_scan_bus(0, &ixp2000_ops, sysdata);
	} else { /* NPU is slave */

		/*
		 * NOTE TO HW DESIGNERS:
		 *
		 * Do NOT make boards like this which have slave devices that scan
		 * the bus and own devices. It is completely against the PCI spec
		 * as it is _NOT_ a peer to peer bus.
		 */
		if(machine_is_ixdp2400())
			pci_scan_bus(0, &ixp2000_ops, sysdata);
	}

	/* enable PCI INTB */
 	*(IXP2000_IRQ_ENABLE_SET) = (1<<15);
	*IXP2000_PCI_XSCALE_INT_ENABLE |= (1<<27) | (1<<26);

	DBG("ixp200_pci_init Done\n");
}

void __init via82c505_init(void *sysdata)
{
	struct pci_bus *bus;

	printk(KERN_DEBUG "PCI: VIA 82c505\n");
	if (!request_region(0xA8,2,"via config")) {
		printk(KERN_WARNING"VIA 82c505: Unable to request region 0xA8\n");
		return;
	}
	if (!request_region(0xCF8,8,"pci config")) {
		printk(KERN_WARNING"VIA 82c505: Unable to request region 0xCF8\n");
		release_region(0xA8, 2);
		return;
	}

	/* Enable compatible Mode */
	outb(0x96,0xA8);
	outb(0x18,0xA9);
	outb(0x93,0xA8);
	outb(0xd0,0xA9);

	pci_scan_bus(0, &via82c505_ops, sysdata);

#ifdef CONFIG_ARCH_SHARK
	/* 
	 * Initialize a fake pci-bus number 1 for the CyberPro
         * on the vlbus
	 */
	bus = pci_scan_bus(1, &dummy_ops, sysdata);
#endif
}

/* --- implementations --- */
int detect_pci22(void){
  
  unsigned int c;
  char counter=0;

  
  pacc = pci_alloc();           /* Get the pci_access structure */
  
  pci_init(pacc);               /* Initialize the PCI library */
  pci_scan_bus(pacc);           /* We want to get the list of devices */


  /* Iterate over all PCI devices */
  for(pci22_dev=pacc->devices; pci22_dev; pci22_dev=pci22_dev->next){
    
    pci_fill_info(pci22_dev, PCI_FILL_IDENT | PCI_FILL_BASES); 
    
    // Detect the specified device
    if( (pci22_dev->vendor_id == PCI22_PCI_VENDOR_ID) && 
	(pci22_dev->device_id == PCI22_PCI_DEVICE_ID) 
	){
      break;
    }

  }
  if (pci22_dev==NULL){
    printf("\n\nERROR: PCI22 card not detected\n\n\n");
    exit(0);
  }


  printf("\n\nPCI22 card detected on %02x:%02x.%d\nVendorID=%04x DeviceID=%04x irq=%d\n",
	 pci22_dev->bus,pci22_dev->dev,
	 pci22_dev->func,pci22_dev->vendor_id,
	 pci22_dev->device_id,
	 pci22_dev->irq);


  printf("\n\n--- Baseaddresses ---\n");
  printf("BAR1 %x\n",pci22_dev->base_addr[0]);
  printf("BAR2 %x\n",pci22_dev->base_addr[1]);
  printf("BAR3 %x\n",pci22_dev->base_addr[2]);
  printf("BAR4 %x\n",pci22_dev->base_addr[3]);
  printf("BAR5 %x\n",pci22_dev->base_addr[4]);
  printf("BAR6 %x\n",pci22_dev->base_addr[6]);
  printf("\n");


  //printPCIDevice(pci22_dev);

/* The baseaddress of the COM20022 is at BAR2 */

//g_pci22dipswitch = pci22_dev->base_addr[1]; //Nonworking
g_pci22base = pci22_dev->base_addr[2];

  /* Close everything */
  pci_cleanup(pacc);

  return 0;
}

static int __init pcibios_init(void)
{
	struct pci_controller *pci_ctrl;
	struct pci_bus *bus;
	int next_busno = 0, i;

	printk("PCI: Probing PCI hardware\n");

	/* Scan all of the recorded PCI controllers.  */
	for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
		pci_ctrl->last_busno = 0xff;
		bus = pci_scan_bus(pci_ctrl->first_busno, pci_ctrl->ops,
				   pci_ctrl);
		if (pci_ctrl->io_resource.flags) {
			unsigned long offs;

			offs = (unsigned long)pci_ctrl->io_space.base;
			pci_ctrl->io_resource.start += offs;
			pci_ctrl->io_resource.end += offs;
			bus->resource[0] = &pci_ctrl->io_resource;
		}
		for (i = 0; i < 3; ++i)
			if (pci_ctrl->mem_resources[i].flags)
				bus->resource[i+1] =&pci_ctrl->mem_resources[i];
		pci_ctrl->bus = bus;
		pci_ctrl->last_busno = bus->subordinate;
		if (next_busno <= pci_ctrl->last_busno)
			next_busno = pci_ctrl->last_busno+1;
	}
	pci_bus_count = next_busno;

	return platform_pcibios_fixup();
}

static int __init l4vpci_x86_init(void)
{
	struct pci_dev *dev = NULL;
	struct pci_bus *bus;
	struct pci_sysdata *sd = kzalloc(sizeof(*sd), GFP_KERNEL);
	if (!sd)
		return -ENOMEM;

	bus = pci_scan_bus(0, &l4vpci_ops, sd);
	if (!bus) {
		pr_err("Failed to scan PCI bus\n");
		return -ENODEV;
	}

	pci_bus_add_devices(bus);

	pr_info("l4vPCI: Using L4-IO for IRQ routing\n");

	for_each_pci_dev(dev)
		l4vpci_irq_enable(dev);

	pcibios_resource_survey();

	return 0;
}

struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata)
{
	if (nr == 0)
		return pci_scan_bus(0, &via82c505_ops, sysdata);

	return NULL;
}

void __init pcibios_init(void)
{
	struct pci_channel *p;
	struct pci_bus *bus;
	int busno;

	/* assign resources */
	busno=0;
	for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
		busno = pciauto_assign_resources(busno, p) + 1;
	}

	/* scan the buses */
	busno = 0;
	for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
		bus = pci_scan_bus(busno, p->pci_ops, p);
		busno = bus->subordinate+1;
	}

	/* fixup irqs (board specific routines) */
	pcibios_fixup_irqs();

	/* 
	 * should we do a fixup of ioport_resource and iomem_resource
	 * based on mips_pci_channels?  
	 * Let us wait and see if this is a common need and whether there
	 * are exceptions.  Until then, each board should adjust them
	 * perhaps in their setup() function.
	 */
}

static int __init pcibios_init(void)
{
	struct pci_channel *p;
	struct pci_bus *bus;
	int busno;

#if 1
	/* assign resources */
	busno = 0;
	for (p = board_pci_channels; p->pci_ops != NULL; p++) {
		busno = pciauto_assign_resources(busno, p) + 1;
	}
#endif

	/* scan the buses */
	busno = 0;
	for (p= board_pci_channels; p->pci_ops != NULL; p++) {
		bus = pci_scan_bus(busno, p->pci_ops, p);
		busno = bus->subordinate+1;
	}

	/* board-specific fixups */
	pcibios_fixup_irqs();

	return 0;
}

/*
 * Initialization. Try all known PCI access methods. Note that we support
 * using both PCI BIOS and direct access: in such cases, we use I/O ports
 * to access config space, but we still keep BIOS order of cards to be
 * compatible with 2.0.X. This should go away some day.
 */
static int __init pcibios_init(void)
{
	ioport_resource.start	= 0xA0000000;
	ioport_resource.end	= 0xDFFFFFFF;
	iomem_resource.start	= 0xA0000000;
	iomem_resource.end	= 0xDFFFFFFF;

	if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
		panic("Unable to insert PCI IOMEM resource\n");
	if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
		panic("Unable to insert PCI IOPORT resource\n");

	if (!pci_probe)
		return 0;

	if (pci_check_direct() < 0) {
		printk(KERN_WARNING "PCI: No PCI bus detected\n");
		return 0;
	}

	printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
	       MEM_PAGING_REG);

	pci_root_bus = pci_scan_bus(0, &pci_direct_ampci, NULL);

	pcibios_irq_init();
	pcibios_fixup_irqs();
	pcibios_resource_survey();
	return 0;
}

static void __init pirq_peer_trick(void)
{
	struct irq_routing_table *rt = pirq_table;
	u8 busmap[256];
	int i;
	struct irq_info *e;

	memset(busmap, 0, sizeof(busmap));
	for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
		e = &rt->slots[i];
#ifdef DEBUG
		{
			int j;
			DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
			for(j=0; j<4; j++)
				DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
			DBG("\n");
		}
#endif
		busmap[e->bus] = 1;
	}
	for(i = 1; i < 256; i++) {
		if (!busmap[i] || pci_find_bus(0, i))
			continue;
		if (pci_scan_bus(i, &pci_root_ops, NULL))
			printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
	}
	pcibios_last_bus = -1;
}

static void __init pirq_peer_trick(void)
{
	struct irq_routing_table *rt = pirq_table;
	u8 busmap[256];
	int i;
	struct irq_info *e;

	memset(busmap, 0, sizeof(busmap));
	for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
		e = &rt->slots[i];
#ifdef DEBUG
		{
			int j;
			DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
			for(j=0; j<4; j++)
				DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
			DBG("\n");
		}
#endif
		busmap[e->bus] = 1;
	}
	for(i=1; i<256; i++)
		/*
		 *  It might be a secondary bus, but in this case its parent is already
		 *  known (ascending bus order) and therefore pci_scan_bus returns immediately.
		 */
		if (busmap[i] && pci_scan_bus(i, pci_root_bus->ops, NULL))
			printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
	pcibios_last_bus = -1;
}

void pci_scan(pci_func_t f, int type) {
	pci_scan_bus(f, type, 0);

	if (!pci_read_field(0, PCI_HEADER_TYPE, 1)) {
		return;
	}

	for (int func = 1; func < 8; ++func) {
		uint32_t dev = pci_box_device(0, 0, func);
		if (pci_read_field(dev, PCI_VENDOR_ID, 2) != PCI_NONE) {
			pci_scan_bus(f, type, func);
		} else {
			break;
		}
	}
}

void pci_scan_func(pci_func_t f, int type, int bus, int slot, int func) {
	uint32_t dev = pci_box_device(bus, slot, func);
	if (type == -1 || type == pci_find_type(dev)) {
		pci_scan_hit(f, dev);
	}
	if (pci_find_type(dev) == PCI_TYPE_BRIDGE) {
		pci_scan_bus(f, type, pci_read_field(dev, PCI_SECONDARY_BUS, 1));
	}
}

static struct pci_bus *soc_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
        return pci_scan_bus(sys->busnr, &soc_pcie_ops, sys);
#else
		return pci_scan_root_bus(NULL, sys->busnr, &soc_pcie_ops, sys,
					&sys->resources);
#endif
}

static int __init pcibios_init(void)
{
	/* The VISWS supports configuration access type 1 only */
	pci_probe = (pci_probe | PCI_PROBE_CONF1) &
		    ~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);

	pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
	pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;

	printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
		"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);

	raw_pci_ops = &pci_direct_conf1;
	pci_scan_bus(pci_bus0, &pci_root_ops, NULL);
	pci_scan_bus(pci_bus1, &pci_root_ops, NULL);
	pci_fixup_irqs(visws_swizzle, visws_map_irq);
	pcibios_resource_survey();
	return 0;
}

/* Exported interface */
int
pci_init(void)
{
	static struct pci_bus root_bus;
	memset(&root_bus, 0, sizeof(root_bus));

	if (platform_pci_init() < 0)
		panic("pci: unable to initial PCI\n");

	return pci_scan_bus(&root_bus);
}

void
pci_init (void)
{
  list_init (&devices);
  list_init (&int_devices);

  num_pci_pages = 0;

  pci_scan_bus (0);
  pci_print_stats ();
}

void __init pcibios_init(void)
{
	/* 
	 * XXX These values below need to change
	 */
	ioport_resource.start = 0xe0000000;
	ioport_resource.end   = 0xe0000000 + 0x20000000 - 1;
	iomem_resource.start  = 0xc0000000;
	iomem_resource.end    = 0xc0000000 + 0x20000000 - 1;

	pci_scan_bus(0, &titan_pci_ops, NULL);
}

void __init pcibios_init(void)
{
	printk("PCI: Probing PCI hardware on host bus 0.\n");

	switch (mips_revision_corid) {
	case MIPS_REVISION_CORID_QED_RM5261:
	case MIPS_REVISION_CORID_CORE_LV:
	case MIPS_REVISION_CORID_CORE_FPGA:
		/*
		 * Due to a bug in the Galileo system controller, we need
		 * to setup the PCI BAR for the Galileo internal registers.
		 * This should be done in the bios/bootprom and will be
		 * fixed in a later revision of YAMON (the MIPS boards
		 * boot prom).
		 */
		GT_WRITE(GT_PCI0_CFGADDR_OFS,
			 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
			 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
			 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
			 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
			 GT_PCI0_CFGADDR_CONFIGEN_BIT );

		/* Perform the write */
		GT_WRITE( GT_PCI0_CFGDATA_OFS, PHYSADDR(GT64120_BASE));

		pci_scan_bus(0, &gt64120_pci_ops, NULL);
		break;

	case MIPS_REVISION_CORID_BONITO64:
	case MIPS_REVISION_CORID_CORE_20K:
		pci_scan_bus(0, &bonito64_pci_ops, NULL);
		break;

	case MIPS_REVISION_CORID_CORE_MSC:
		pci_scan_bus(0, &msc_pci_ops, NULL);
		break;
	}

	malta_fixup();
}

void __init pcibios_init(void)
{
	struct pci_ops *ops = &bridge_pci_ops;
	int	i;

	ioport_resource.end = ~0UL;
	iomem_resource.end = ~0UL;

	for (i=0; i<num_bridges; i++) {
		printk("PCI: Probing PCI hardware on host bus %2d.\n", i);
		pci_scan_bus(i, ops, NULL);
	}
}