/*
 * "unmap" the BAR referred to by argument. If more than one place has mapped it
 * we just decrement the reference counter so nothing untoward happens.
 */
void
vga_pci_bar_unmap(struct vga_pci_bar *bar)
{
	if (bar != NULL && bar->mapped != 0) {
		if (--bar->mapped == 0)
			bus_space_unmap(bar->bst, bar->bsh, bar->size);
	}
}

void
_isa_dmadestroy(struct isa_dma_state *ids)
{
	if (!ids->ids_initialized)
		return;

	_isa_dmacascade_stop(ids, 4);

	/*
	 * Unmap the registers used by the ISA DMA controller.
	 */
	bus_space_unmap(ids->ids_bst, ids->ids_dmapgh, 0xf);
	bus_space_unmap(ids->ids_bst, ids->ids_dma2h, DMA2_IOSIZE);
	bus_space_unmap(ids->ids_bst, ids->ids_dma1h, DMA1_IOSIZE);

	ids->ids_initialized = 0;
}

/* Unmap the I/O ports */
void
ad1848_isa_unmap(struct ad1848_isa_softc *isc)
{
	struct ad1848_softc *sc;

	sc = &isc->sc_ad1848;
	bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT);
}

void
imxahci_attach(struct device *parent, struct device *self, void *args)
{
	struct armv7_attach_args *aa = args;
	struct imxahci_softc *imxsc = (struct imxahci_softc *) self;
	struct ahci_softc *sc = &imxsc->sc;
	uint32_t timeout = 0x100000;

	sc->sc_iot = aa->aa_iot;
	sc->sc_ios = aa->aa_dev->mem[0].size;
	sc->sc_dmat = aa->aa_dmat;

	if (bus_space_map(sc->sc_iot, aa->aa_dev->mem[0].addr,
	    aa->aa_dev->mem[0].size, 0, &sc->sc_ioh))
		panic("imxahci_attach: bus_space_map failed!");

	sc->sc_ih = arm_intr_establish(aa->aa_dev->irq[0], IPL_BIO,
	    ahci_intr, sc, sc->sc_dev.dv_xname);
	if (sc->sc_ih == NULL) {
		printf(": unable to establish interrupt\n");
		goto unmap;
	}

	/* power it up */
	imxccm_enable_sata();
	delay(100);

	/* power phy up */
	imxiomuxc_enable_sata();

	/* setup */
	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYCR,
	    bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYCR) & ~SATA_P0PHYCR_TEST_PDDQ);

	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_GHC, SATA_GHC_HR);

	while (!bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_VERSIONR));

	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_CAP,
	    bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_CAP) | SATA_CAP_SSS);

	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_PI, 1);

	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_TIMER1MS, imxccm_get_ahbclk());

	while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_P0SSTS) & 0xF) && timeout--);

	if (ahci_attach(sc) != 0) {
		/* error printed by ahci_attach */
		goto irq;
	}

	return;
irq:
	arm_intr_disestablish(sc->sc_ih);
unmap:
	bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
}

int
macfb_obio_match(struct device *parent, void *vcf, void *aux)
{
	struct obio_attach_args *oa = (struct obio_attach_args *)aux;
	bus_space_handle_t bsh;
	static int found;

	if (found != 0)
		return (0);

	found = 1;

        switch (current_mac_model->class) {
	case MACH_CLASSQ2:
		if (current_mac_model->machineid != MACH_MACLC575)
			break;

		/*
		 * Note:  the only system in this class that does not have
		 * the Valkyrie chip -- at least, that we know of -- is
		 * the Performa/LC 57x series.  This system has a version
		 * of the DAFB controller, instead.
		 *
		 * If this assumption proves false, we'll have to be more
		 * intelligent here.
		 */
		/*FALLTHROUGH*/
	case MACH_CLASSQ:
		/*
		 * Assume DAFB for all of these, unless we can't
		 * access the memory.
		 */
		if (bus_space_map(oa->oa_tag, DAFB_CONTROL_BASE, 0x120, 0,
		    &bsh) != 0)
			return (0);

		if (mac68k_bus_space_probe(oa->oa_tag, bsh, 0x1c, 4) == 0 ||
		    mac68k_bus_space_probe(oa->oa_tag, bsh, 0x104, 4) == 0)
			found = 0;

		bus_space_unmap(oa->oa_tag, bsh, 0x120);
		break;
	case MACH_CLASSAV:
		break;
	case MACH_CLASSIIci:
	case MACH_CLASSIIsi:
		if (mac68k_vidlen == 0 ||
		    (via2_reg(rMonitor) & RBVMonitorMask) == RBVMonIDNone)
			found = 0;
		break;
	default:
		if (mac68k_vidlen == 0)
			found = 0;
		break;
	}

	return (found);
}

/*
 * Attach the peripheral bus.
 */
static void
pbus_attach(struct device *parent, struct device *self, void *aux)
{
	struct plb_attach_args *paa = aux;
	struct pbus_attach_args pba;
	int i;
#if NPCKBC > 0
	bus_space_handle_t ioh_fpga;
	bus_space_tag_t iot_fpga = &pbus_tag;
	uint8_t fpga_reg;
#endif

	printf("\n");

	if (bus_space_init(&pbus_tag, "pbus", NULL, 0))
		panic("pbus_attach: can't init tag");

	for (i = 0; pbus_devs[i].name != NULL; i++) {
		pba.pb_name = pbus_devs[i].name;
		pba.pb_addr = pbus_devs[i].addr;
		pba.pb_irq = pbus_devs[i].irq;
		pba.pb_bt = &pbus_tag;
		pba.pb_dmat = paa->plb_dmat;

		(void) config_found_sm(self, &pba, pbus_print, pbus_submatch);
	}

#if NPCKBC > 0
	/* Configure FPGA */
	if (bus_space_map(iot_fpga, FPGA_BASE, FPGA_SIZE, 0, &ioh_fpga)) {
		printf("pbus_attach: can't map FPGA\n");
		/* XXX - disable keyboard probe? */
	} else {
		/* Use separate interrupts for keyboard and mouse */
		fpga_reg = bus_space_read_1(iot_fpga, ioh_fpga, FPGA_BRDC);
		fpga_reg |= FPGA_BRDC_INT;
		bus_space_write_1(iot_fpga, ioh_fpga, FPGA_BRDC, fpga_reg);

		/* Set interrupts to active high */
		fpga_reg = bus_space_read_1(iot_fpga, ioh_fpga, FPGA_INT_POL);
		fpga_reg |= (FPGA_IRQ_KYBD | FPGA_IRQ_MOUSE);
		bus_space_write_1(iot_fpga, ioh_fpga, FPGA_INT_POL, fpga_reg);

		/* Set interrupts to level triggered */
		fpga_reg = bus_space_read_1(iot_fpga, ioh_fpga, FPGA_INT_TRIG);
		fpga_reg |= (FPGA_IRQ_KYBD | FPGA_IRQ_MOUSE);
		bus_space_write_1(iot_fpga, ioh_fpga, FPGA_INT_TRIG, fpga_reg);

		/* Enable interrupts */
		fpga_reg = bus_space_read_1(iot_fpga, ioh_fpga, FPGA_INT_ENABLE);
		fpga_reg |= (FPGA_IRQ_KYBD | FPGA_IRQ_MOUSE);
		bus_space_write_1(iot_fpga, ioh_fpga, FPGA_INT_ENABLE, fpga_reg);

		bus_space_unmap(&iot_fpga, ioh_fpga, 2);
	}
#endif

}

void
com_isa_attach(device_t parent, device_t self, void *aux)
{
	struct com_isa_softc *isc = device_private(self);
	struct com_softc *sc = &isc->sc_com;
	int iobase, irq;
	bus_space_tag_t iot;
	bus_space_handle_t ioh;
	struct isa_attach_args *ia = aux;
#ifdef COM_HAYESP
	int	hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 };
	int	*hayespp;
#endif

	/*
	 * We're living on an isa.
	 */
	iobase = ia->ia_io[0].ir_addr;
	iot = ia->ia_iot;

	if (!com_is_console(iot, iobase, &ioh) &&
	    bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
		printf(": can't map i/o space\n");
		return;
	}

	sc->sc_dev = self;

	COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);

	sc->sc_frequency = COM_FREQ;
	irq = ia->ia_irq[0].ir_irq;

#ifdef COM_HAYESP
	for (hayespp = hayesp_ports; *hayespp != 0; hayespp++) {
		bus_space_handle_t	hayespioh;
#define	HAYESP_NPORTS	8
		if (bus_space_map(iot, *hayespp, HAYESP_NPORTS, 0, &hayespioh))
			continue;
		if (com_isa_isHAYESP(hayespioh, sc)) {
			break;
		}
		bus_space_unmap(iot, hayespioh, HAYESP_NPORTS);
	}
#endif

	com_attach_subr(sc);

	if (!pmf_device_register1(self, com_isa_suspend, com_isa_resume,
	    com_cleanup))
		aprint_error_dev(self, "couldn't establish power handler\n");

	isc->sc_ic = ia->ia_ic;
	isc->sc_irq = irq;
	isc->sc_ih = isa_intr_establish_xname(ia->ia_ic, irq, IST_EDGE,
	    IPL_SERIAL, comintr, sc, device_xname(sc->sc_dev));
}

int
lm_isa_detach(device_t self, int flags)
{
	struct lm_isa_softc *sc = device_private(self);

	lm_detach(&sc->lmsc);
	bus_space_unmap(sc->lm_iot, sc->lm_ioh, 8);
	return 0;
}

static int
fdc_isa_detach(device_t self, int flags)
{
	int rc;
	struct fdc_isa_softc *isc = device_private(self);
	struct fdc_softc *fdc = &isc->sc_fdc;

	if ((rc = fdcdetach(self, flags)) != 0)
		return rc;

	isa_intr_disestablish(fdc->sc_ic, fdc->sc_ih);

	bus_space_unmap(fdc->sc_iot, fdc->sc_fdctlioh, 1);

	bus_space_unmap(fdc->sc_iot, isc->sc_baseioh, 6 /* FDC_NPORT */);

	return 0;
}

void
drm_iounmap(struct drm_device *dev, struct drm_local_map *map)
{
	if (map->lm_data.bus_space.bus_map != NULL) {
		bus_space_unmap(map->lm_data.bus_space.bst,
		    map->lm_data.bus_space.bsh, map->size);
		map->lm_data.bus_space.bus_map = NULL;
	}
}

static int
space_unmap(lua_State *L)
{
  bus_space_unmap(*(bus_space_tag_t *) lua_touserdata(L, -3),
		  *(bus_space_handle_t *) lua_touserdata(L, -2), 
		  lua_tointeger(L, -1));
  lua_pop(L, 3);
  return 0;
}

static void
args_unmap(int *num_mappings, struct isic_io_map *maps)
{
	int i, n;
	for (i = 0, n = *num_mappings; i < n; i++)
        	if (maps[i].size)
			bus_space_unmap(maps[i].t, maps[i].h, maps[i].size);
	*num_mappings = 0;
}

static int
smsc_detach(device_t self, int flags)
{
	struct smsc_softc *sc = device_private(self);

	sysmon_envsys_unregister(sc->sc_sme);
	bus_space_unmap(sc->sc_iot, sc->sc_ioh, 2);
	return 0;
}

void
mfi_pci_attach(struct device *parent, struct device *self, void *aux)
{
	struct mfi_softc	*sc = (struct mfi_softc *)self;
	struct pci_attach_args	*pa = aux;
	const struct mfi_pci_device *mpd;
	pci_intr_handle_t	ih;
	bus_size_t		size;
	pcireg_t		reg;
	int			regbar;

	mpd = mfi_pci_find_device(pa);
	if (mpd == NULL) {
		printf(": can't find matching pci device\n");
		return;
	}

	if (mpd->mpd_iop == MFI_IOP_GEN2 || mpd->mpd_iop == MFI_IOP_SKINNY)
		regbar = MFI_BAR_GEN2;
	else
		regbar = MFI_BAR;

	reg = pci_mapreg_type(pa->pa_pc, pa->pa_tag, regbar);
	if (pci_mapreg_map(pa, regbar, reg, 0,
	    &sc->sc_iot, &sc->sc_ioh, NULL, &size, MFI_PCI_MEMSIZE)) {
		printf(": can't map controller pci space\n");
		return;
	}

	sc->sc_dmat = pa->pa_dmat;

	if (pci_intr_map(pa, &ih) != 0) {
		printf(": can't map interrupt\n");
		goto unmap;
	}
	printf(": %s\n", pci_intr_string(pa->pa_pc, ih));

	sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, mfi_intr, sc,
	    sc->sc_dev.dv_xname);
	if (!sc->sc_ih) {
		printf("%s: can't establish interrupt\n", DEVNAME(sc));
		goto unmap;
	}

	if (mfi_attach(sc, mpd->mpd_iop)) {
		printf("%s: can't attach\n", DEVNAME(sc));
		goto unintr;
	}

	return;
unintr:
	pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
	sc->sc_ih = NULL;
unmap:
	bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
}

/*
 * Probe for the SMSC Super I/O chip
 */
static int
smsc_match(device_t parent, cfdata_t match, void *aux)
{
	bus_space_handle_t ioh;
	struct isa_attach_args *ia = aux;
	int rv;
	uint8_t cr;

	/* Must supply an address */
	if (ia->ia_nio < 1)
		return 0;

	if (ISA_DIRECT_CONFIG(ia))
		return 0;

	if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
		return 0;

	if (bus_space_map(ia->ia_iot, ia->ia_io[0].ir_addr, 2, 0, &ioh))
		return 0;

	/* To get the device ID we must enter config mode... */
	bus_space_write_1(ia->ia_iot, ioh, SMSC_ADDR, SMSC_CONFIG_START);

	/* Then select the device id register */
	cr = smsc_readreg(ia->ia_iot, ioh, SMSC_DEVICE_ID);

	/* Exit config mode, apparently this is important to do */
	bus_space_write_1(ia->ia_iot, ioh, SMSC_ADDR, SMSC_CONFIG_END);

	switch (cr) {
	case SMSC_ID_47B397:
	case SMSC_ID_SCH5307NS:
	case SMSC_ID_SCH5317:
		rv = 1;
		break;
	default:
		rv = 0;
		break;
	}

	DPRINTF(("smsc: rv = %d, cr = %x\n", rv, cr));

	bus_space_unmap(ia->ia_iot, ioh, 2);

	if (rv) {
		ia->ia_nio = 1;
		ia->ia_io[0].ir_size = 2;

		ia->ia_niomem = 0;
		ia->ia_nirq = 0;
		ia->ia_ndrq = 0;
	}

	return rv;
}

int
imxahci_detach(struct device *self, int flags)
{
	struct imxahci_softc *imxsc = (struct imxahci_softc *) self;
	struct ahci_softc *sc = &imxsc->sc;

	ahci_detach(sc, flags);
	bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
	return 0;
}

/* Probe for TPM using legacy interface. */
int
tpm_legacy_probe(bus_space_tag_t iot, bus_addr_t iobase)
{
	bus_space_handle_t ioh;
	u_int8_t r, v;
	int i, rv = 0;
	char id[8];

	if (!tpm_enabled || iobase == -1)
		return 0;

	if (bus_space_map(iot, iobase, 2, 0, &ioh))
		return 0;

	v = bus_space_read_1(iot, ioh, 0);
	if (v == 0xff) {
		bus_space_unmap(iot, ioh, 2);
		return 0;
	}
	r = bus_space_read_1(iot, ioh, 1);

	for (i = sizeof(id); i--; )
		id[i] = tpm_legacy_in(iot, ioh, TPM_ID + i);

#ifdef TPM_DEBUG
	printf("tpm_legacy_probe %.4s %d.%d.%d.%d\n",
	    &id[4], id[0], id[1], id[2], id[3]);
#endif
	/*
	 * The only chips using the legacy interface we are aware of are
	 * by Atmel.  For other chips more signature would have to be added.
	 */
	if (!bcmp(&id[4], "ATML", 4))
		rv = 1;

	if (!rv) {
		bus_space_write_1(iot, ioh, r, 1);
		bus_space_write_1(iot, ioh, v, 0);
	}
	bus_space_unmap(iot, ioh, 2);

	return rv;
}

void    
platform_mp_start_ap(void)
{
	bus_space_handle_t scu_handle;
	bus_space_handle_t ocm_handle;
	uint32_t scu_ctrl;

	/* Map in SCU control register. */
	if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4,
			  0, &scu_handle) != 0)
		panic("platform_mp_start_ap: Couldn't map SCU config reg\n");

	/* Set SCU enable bit. */
	scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0);
	scu_ctrl |= SCU_CONTROL_ENABLE;
	bus_space_write_4(fdtbus_bs_tag, scu_handle, 0, scu_ctrl);

	bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);

	/* Map in magic location to give entry address to CPU1. */
	if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
	    0, &ocm_handle) != 0)
		panic("platform_mp_start_ap: Couldn't map OCM\n");

	/* Write start address for CPU1. */
	bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,
	    pmap_kextract((vm_offset_t)mpentry));

	bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4);

	/*
	 * The SCU is enabled above but I think the second CPU doesn't
	 * turn on filtering until after the wake-up below. I think that's why
	 * things don't work if I don't put these cache ops here.  Also, the
	 * magic location, 0xfffffff0, isn't in the SCU's filtering range so it
	 * needs a write-back too.
	 */
	cpu_idcache_wbinv_all();
	cpu_l2cache_wbinv_all();

	/* Wake up CPU1. */
	armv7_sev();
}

static int
slhci_intio_match(device_t parent, cfdata_t cf, void *aux)
{
	struct intio_attach_args *ia = aux;
	bus_space_tag_t iot = ia->ia_bst;
	bus_space_handle_t ioh;
	bus_space_handle_t nch;
	int nc_addr;
	int nc_size;

	if (ia->ia_addr == INTIOCF_ADDR_DEFAULT)
		ia->ia_addr = SLHCI_INTIO_ADDR1;
	if (ia->ia_intr == INTIOCF_INTR_DEFAULT)
		ia->ia_intr = SLHCI_INTIO_INTR1;

	/* fixed parameters */
	if ( !(ia->ia_addr == SLHCI_INTIO_ADDR1 &&
	       ia->ia_intr == SLHCI_INTIO_INTR1   ) &&
	     !(ia->ia_addr == SLHCI_INTIO_ADDR2 &&
	       ia->ia_intr == SLHCI_INTIO_INTR2   ) )
		return 0;

	/* Whether the control port is accessible or not */
	nc_addr = ia->ia_addr + NEREID_ADDR_OFFSET;
	nc_size = 0x02;
	if (badbaddr(INTIO_ADDR(nc_addr)))
		return 0;

	/* Map two I/O spaces */
	ia->ia_size = SL11_PORTSIZE * 2;
	if (bus_space_map(iot, ia->ia_addr, ia->ia_size,
			BUS_SPACE_MAP_SHIFTED, &ioh))
		return 0;

	if (bus_space_map(iot, nc_addr, nc_size,
			BUS_SPACE_MAP_SHIFTED, &nch))
		return 0;

	bus_space_unmap(iot, ioh, ia->ia_size);
	bus_space_unmap(iot, nch, nc_size);

	return 1;
}

int
tsrtc_match(device_t parent, cfdata_t cf, void *aux)
{
	struct tspld_attach_args *aa = aux;
	struct tsrtc_softc tsrtc, *tsc;
	struct mc146818_softc *sc;
	unsigned int t1, t2;
	static int found = -1;

	if (found != -1)
		return found;

	tsc = &tsrtc;
	sc = &tsc->sc_mc;
	tsc->sc_iot = aa->ta_iot;
	if (bus_space_map(tsc->sc_iot, TS7XXX_IO8_HWBASE + TS7XXX_RTCIDX, 1, 0,
		 &tsc->sc_idxh))
		return (0);
	if (bus_space_map(tsc->sc_iot, TS7XXX_IO8_HWBASE + TS7XXX_RTCDAT, 1, 0,
		 &tsc->sc_dath))
		return (0);

	/* Read from the seconds counter. */
	t1 = FROMBCD(tsrtc_read(sc, MC_SEC));
	if (t1 > 59)
		goto unmap;

	/* Wait, then look again. */
	DELAY(1100000);
	t2 = FROMBCD(tsrtc_read(sc, MC_SEC));
	if (t2 > 59)
		goto unmap;

        /* If [1,2) seconds have passed since, call it a clock. */
	if ((t1 + 1) % 60 == t2 || (t1 + 2) % 60 == t2)
		found = 1;

 unmap:
	bus_space_unmap(tsc->sc_iot, tsc->sc_idxh, 1);
	bus_space_unmap(tsc->sc_iot, tsc->sc_dath, 1);

	return (found);
}