/*
 * cfi_cmd - write a CFI command word.
 *
 * The offset 'off' is given for 64-bit port width and will be scaled
 * down to the actual port width of the chip.
 * The command word will be constructed out of 'val' regarding port- and
 * chip width.
 */
void
cfi_cmd(struct cfi * const cfi, bus_size_t off, uint32_t val)
{
	const bus_space_tag_t bst = cfi->cfi_bst;
	bus_space_handle_t bsh = cfi->cfi_bsh;
	uint64_t cmd;
	int cw, pw;

	off >>= 3 - cfi->cfi_portwidth;

	pw = 1 << cfi->cfi_portwidth;
	cw = 1 << cfi->cfi_chipwidth;
	cmd = 0;
	while (pw > 0) {
		cmd <<= cw << 3;
		cmd += val;
		pw -= cw;
	}

	DPRINTF(("%s: %p %x %x %" PRIx64 "\n", __func__, bst, bsh, off, cmd));

	switch (cfi->cfi_portwidth) {
	case 0:
		bus_space_write_1(bst, bsh, off, cmd);
		break;
	case 1:
		bus_space_write_2(bst, bsh, off, cmd);
		break;
	case 2:
		bus_space_write_4(bst, bsh, off, cmd);
		break;
#ifdef NOTYET
	case 3:
		bus_space_write_8(bst, bsh, off, cmd);
		break;
#endif
	default:
		panic("%s: bad portwidth %d bytes\n",
			__func__, 1 << cfi->cfi_portwidth);
	}
}

int
tpm_request_locality(struct tpm_softc *sc, int l)
{
	u_int32_t r;
	int to, rv;

	if (l != 0)
		return EINVAL;

	if ((bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_ACCESS) &
	    (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) ==
	    (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY))
		return 0;

	bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_ACCESS,
	    TPM_ACCESS_REQUEST_USE);

	to = tpm_tmotohz(TPM_ACCESS_TMO);

	while ((r = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_ACCESS) &
	    (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) !=
	    (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY) && to--) {
		rv = tsleep(sc->sc_init, PRIBIO | PCATCH, "tpm_locality", 1);
		if (rv &&  rv != EWOULDBLOCK) {
#ifdef TPM_DEBUG
			printf("tpm_request_locality: interrupted %d\n", rv);
#endif
			return rv;
		}
	}

	if ((r & (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) !=
	    (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) {
#ifdef TPM_DEBUG
		printf("tpm_request_locality: access %b\n", r, TPM_ACCESS_BITS);
#endif
		return EBUSY;
	}

	return 0;
}

static void
dmac_init_channels(struct dmac_softc *sc)
{
	int i;

	DPRINTF(3, ("dmac_init_channels\n"));
	for (i=0; i<DMAC_NCHAN; i++) {
		sc->sc_channels[i].ch_channel = i;
		sc->sc_channels[i].ch_name[0] = 0;
		sc->sc_channels[i].ch_softc = sc;
		bus_space_subregion(sc->sc_bst, sc->sc_bht,
				    DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE,
				    &sc->sc_channels[i].ch_bht);
		sc->sc_channels[i].ch_xfer.dx_dmamap = 0;
		/* reset the status register */
		bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht,
				  DMAC_REG_CSR, 0xff);
	}

	return;
}

/*---------------------------------------------------------------------------*
 *	AVM read register routines
 *---------------------------------------------------------------------------*/
static u_int8_t
avm_pnp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
{
	u_char reg_bank;
	bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
	bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]); 

	switch (what) {
		case ISIC_WHAT_ISAC:
			reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
			/* set the register bank */
			bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
			return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
				(offs & ISAC_REGSET_MASK)));
		case ISIC_WHAT_HSCXA:
			return hscx_read_reg(0, offs, sc);
		case ISIC_WHAT_HSCXB:
			return hscx_read_reg(1, offs, sc);
	}
	return 0;
}

static void
mv_nand_write_buf(device_t dev, void* buf, uint32_t len)
{
	struct mv_nand_softc *sc;
	int i;
	uint8_t *b = (uint8_t*)buf;

	sc = device_get_softc(dev);

	for (i = 0; i < len; i++) {
#ifdef NAND_DEBUG
		if (!(i % 16))
			printf("%s", i == 0 ? "mv_nand:\n" : "\n");
		printf(" %x", b[i]);
		if (i == len - 1)
			printf("\n");
#endif
		bus_space_write_1(sc->sc_tag, sc->sc_handle, MV_NAND_DATA,
		    b[i]);
	}
}

int
glxpcib_smb_initiate_xfer(void *arg, i2c_addr_t addr, int flags)
{
	struct glxpcib_softc *sc = arg;
	int error, dir;

	/* Issue start condition */
	glxpcib_smb_send_start(sc, flags);

	/* Wait for bus mastership */
	if ((error = glxpcib_smb_wait(sc, AMD5536_SMB_STS_MASTER |
	    AMD5536_SMB_STS_SDAST, flags)) != 0)
		return (error);

	/* Send address byte */
	dir = (flags & I2C_F_READ ? 1 : 0);
	bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, AMD5536_SMB_SDA,
	    (addr << 1) | dir);

	return (0);
}

void
dl10019_mii_statchg(struct device *self)
{
	struct dp8390_softc *sc = (void *) self;
	struct ne2000_softc *nsc = (void *) self;

	/*
	 * Disable collision detection on the DL10022 if
	 * we are on a full-duplex link.
	 */
	if (nsc->sc_type == NE2000_TYPE_DL10022) {
		u_int8_t diag;

		if (sc->sc_mii.mii_media_active & IFM_FDX)
			diag = DL0_DIAG_NOCOLLDETECT;
		else
			diag = 0;
		bus_space_write_1(sc->sc_regt, sc->sc_regh,
		    NEDL_DL0_DIAG, diag);
	}
}

void
vga_loadchars(struct vga_handle *vh, int fontset, int first, int num, int lpc,
    char *data)
{
	int offset, i, j, s;

	/* fontset number swizzle done in vga_setfontset() */
	offset = (fontset << 13) | (first << 5);

	s = splhigh();
	fontram(vh);

	for (i = 0; i < num; i++)
		for (j = 0; j < lpc; j++)
			bus_space_write_1(vh->vh_memt, vh->vh_allmemh,
					  offset + (i << 5) + j,
					  data[i * lpc + j]);

	textram(vh);
	splx(s);
}

static int
stg_msg(struct stg_softc *sc, struct targ_info *ti, u_int msg)
{
	bus_space_tag_t iot = sc->sc_iot;
	bus_space_handle_t ioh = sc->sc_ioh;
	struct stg_targ_info *sti = (void *) ti;
	u_int period;

	if ((msg & SCSI_LOW_MSG_WIDE) != 0)
	{
		if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
		{
			ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
			return EINVAL;
		}
		return 0;
	}

	if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
		return 0;

	period = ti->ti_maxsynch.period;
	period = period << 2;
	if (period >= 200)
	{
		sti->sti_reg_synch = (period - 200) / 50;
		if (period % 50)
			sti->sti_reg_synch ++;
		sti->sti_reg_synch |= SSCTL_SYNCHEN;
	}
	else if (period >= 100)
	{
		sti->sti_reg_synch = (period - 100) / 50;
		if (period % 50)
			sti->sti_reg_synch ++;
		sti->sti_reg_synch |= SSCTL_SYNCHEN | SSCTL_FSYNCHEN;
	}
	bus_space_write_1(iot, ioh, tmc_ssctl, sti->sti_reg_synch);
	return 0;
}

static void
thunder_pem_write_config(device_t dev, u_int bus, u_int slot,
    u_int func, u_int reg, uint32_t val, int bytes)
{
	uint64_t offset;
	struct thunder_pem_softc *sc;
	bus_space_tag_t	t;
	bus_space_handle_t h;

	if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
	    (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
		return;

	sc = device_get_softc(dev);

	/* Calculate offset */
	offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
	    (func << PEM_FUNC_SHIFT);
	t = sc->reg_bst;
	h = sc->pem_sli_base;

	bus_space_map(sc->reg_bst, sc->sli_window_base + offset,
	    PCIE_REGMAX, 0, &h);

	switch (bytes) {
	case 1:
		bus_space_write_1(t, h, reg, val);
		break;
	case 2:
		bus_space_write_2(t, h, reg, htole16(val));
		break;
	case 4:
		bus_space_write_4(t, h, reg, htole32(val));
		break;
	default:
		break;
	}

	bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX);
}

/* Setup TPM using TIS 1.2 interface. */
int
tpm_tis12_init(struct tpm_softc *sc, int irq, const char *name)
{
	u_int32_t r;
	int i;

	r = bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INTF_CAPABILITIES);
#ifdef TPM_DEBUG
	printf(" caps=%b ", r, TPM_CAPBITS);
#endif
	if ((r & TPM_CAPSREQ) != TPM_CAPSREQ ||
	    !(r & (TPM_INTF_INT_EDGE_RISING | TPM_INTF_INT_LEVEL_LOW))) {
		printf(": capabilities too low (caps=%b)\n", r, TPM_CAPBITS);
		return 1;
	}
	sc->sc_capabilities = r;

	sc->sc_devid = bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_ID);
	sc->sc_rev = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_REV);

	for (i = 0; tpm_devs[i].devid; i++)
		if (tpm_devs[i].devid == sc->sc_devid)
			break;

	if (tpm_devs[i].devid)
		printf(": %s rev 0x%x\n", tpm_devs[i].name, sc->sc_rev);
	else
		printf(": device 0x%08x rev 0x%x\n", sc->sc_devid, sc->sc_rev);

	if (tpm_tis12_irqinit(sc, irq, i))
		return 1;

	if (tpm_request_locality(sc, 0))
		return 1;

	/* Abort whatever it thought it was doing. */
	bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY);

	return 0;
}

/*
 * (un)block input via hw flowcontrol
 */
void
ucom_hwiflow(struct ucom_softc *sc)
{
	DPRINTF(("ucom_hwiflow:\n"));
#if 0
XXX
	bus_space_tag_t iot = sc->sc_iot;
	bus_space_handle_t ioh = sc->sc_ioh;

	if (sc->sc_mcr_rts == 0)
		return;

	if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) {
		CLR(sc->sc_mcr, sc->sc_mcr_rts);
		CLR(sc->sc_mcr_active, sc->sc_mcr_rts);
	} else {
		SET(sc->sc_mcr, sc->sc_mcr_rts);
		SET(sc->sc_mcr_active, sc->sc_mcr_rts);
	}
	bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr_active);
#endif
}

static int
slhci_isa_match(device_t parent, cfdata_t cf, void *aux)
{
	struct isa_attach_args *ia = aux;
	bus_space_tag_t iot = ia->ia_iot;
	bus_space_handle_t ioh;
	int result = 0;
	uint8_t sltype;

	if (bus_space_map(iot, ia->ia_io[0].ir_addr, SL11_PORTSIZE, 0, &ioh))
		goto out;

	bus_space_write_1(iot, ioh, SL11_IDX_ADDR, SL11_REV);
	sltype = SL11_GET_REV(bus_space_read_1(iot, ioh, SL11_IDX_DATA));

	result = slhci_supported_rev(sltype);

	bus_space_unmap(iot, ioh, SL11_PORTSIZE);

 out:
	return (result);
}

/*
 * Bus access methods for MI mk48txx driver.
 */
uint8_t
mkclock_isa_nvrd(bus_space_tag_t iot, bus_space_handle_t ioh, int off)
{
	uint8_t datum;
	int s;

#ifdef DEBUG
	printf("mkclock_isa_nvrd(%d)", off);
#endif

	s = splclock();
	bus_space_write_1(iot, ioh, MKCLOCK_STB0, off & 0xff);
	bus_space_write_1(iot, ioh, MKCLOCK_STB1, off >> 8);
	datum = bus_space_read_1(iot, ioh, MKCLOCK_DATA);
	splx(s);

#ifdef DEBUG
	printf(" -> %02x\n", datum);
#endif

	return (datum);
}

int
pchbactivate(struct device *self, int act)
{
	struct pchb_softc *sc = (struct pchb_softc *)self;
	int rv = 0;

	switch (act) {
	case DVACT_RESUME:
		/* re-enable RNG, if we have it */
		if (sc->sc_rng_active)
			bus_space_write_1(sc->sc_bt, sc->sc_bh,
			    I82802_RNG_HWST,
			    bus_space_read_1(sc->sc_bt, sc->sc_bh,
			    I82802_RNG_HWST) | I82802_RNG_HWST_ENABLE);
		rv = config_activate_children(self, act);
		break;
	default:
		rv = config_activate_children(self, act);
		break;
	}
	return (rv);
}

static void
siemens_isurf_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data)
{
    bus_space_tag_t t = sc->sc_maps[0].t;
    bus_space_handle_t h = sc->sc_maps[0].h;
    switch (what) {
    case ISIC_WHAT_ISAC:
        bus_space_write_1(t, h, SIE_ISURF_OFF_ALE, IPAC_ISAC_OFF+offs);
        bus_space_write_1(t, h, SIE_ISURF_OFF_RW, data);
        break;
    case ISIC_WHAT_HSCXA:
        bus_space_write_1(t, h, SIE_ISURF_OFF_ALE, IPAC_HSCXA_OFF+offs);
        bus_space_write_1(t, h, SIE_ISURF_OFF_RW, data);
        break;
    case ISIC_WHAT_HSCXB:
        bus_space_write_1(t, h, SIE_ISURF_OFF_ALE, IPAC_HSCXB_OFF+offs);
        bus_space_write_1(t, h, SIE_ISURF_OFF_RW, data);
        break;
    case ISIC_WHAT_IPAC:
        bus_space_write_1(t, h, SIE_ISURF_OFF_ALE, IPAC_IPAC_OFF+offs);
        bus_space_write_1(t, h, SIE_ISURF_OFF_RW, data);
        break;
    }
}

void
berkwdt_attach(struct device *parent, struct device *self, void *aux)
{
	struct berkwdt_softc *sc = (struct berkwdt_softc *)self;
	struct pci_attach_args *const pa = (struct pci_attach_args *)aux;
	bus_size_t iosize;
	u_int8_t reg;

	/* retrieve the I/O region (BAR 0) */
	if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0,
	    &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0) != 0) {
		printf(": couldn't find PCI I/O region\n");
		return;
	}

	/* Check for reboot by the card */
	reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PCWD_PCI_CS1);
	if (reg & WD_PCI_WTRP) {
		printf(", warning: watchdog triggered");

		if (reg & WD_PCI_TTRP)
			printf(", overheat detected");

		/* clear trip status & LED and keep mode of relay 2 */
		reg &= WD_PCI_R2DS;
		reg |= WD_PCI_WTRP;
		bus_space_write_1(sc->sc_iot, sc->sc_ioh, PCWD_PCI_CS1, reg);
	}

	printf("\n");

	/* ensure that the watchdog is disabled */
	berkwdt_stop(sc);
	sc->sc_period = 0;

	/* register with the watchdog framework */
	wdog_register(berkwdt_set_timeout, sc);
}

static int
joy_isa_probe(device_t parent, cfdata_t match, void *aux)
{
	struct isa_attach_args *ia = aux;
	bus_space_tag_t iot = ia->ia_iot;
	bus_space_handle_t ioh;
	int rval = 0;

	if (ia->ia_nio < 1)
		return 0;

	if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
		return 0;

	if (bus_space_map(iot, ia->ia_io[0].ir_addr, JOY_NPORTS, 0, &ioh))
		return 0;

#ifdef WANT_JOYSTICK_CONNECTED
	bus_space_write_1(iot, ioh, 0, 0xff);
	DELAY(10000);		/* 10 ms delay */
	if ((bus_space_read_1(iot, ioh, 0) & 0x0f) != 0x0f)
		rval = 1;
#else
	rval = 1;
#endif

	bus_space_unmap(iot, ioh, JOY_NPORTS);

	if (rval) {
		ia->ia_nio = 1;
		ia->ia_io[0].ir_size = JOY_NPORTS;

		ia->ia_niomem = 0;
		ia->ia_nirq = 0;
		ia->ia_ndrq = 0;
	}
	return rval;
}

static int
arckbd_send(device_t self, int data, enum arckbd_state newstate, int waitok)
{
	struct arckbd_softc *sc = device_private(self);
	int s, res;
	bus_space_tag_t bst = sc->sc_bst;
	bus_space_handle_t bsh = sc->sc_bsh;

	s = spltty();
	if (waitok) {
		while (!ioc_irq_status(IOC_IRQ_STX))
			if ((sc->sc_flags & AKF_POLLING) == 0) {
				res = tsleep(arckbd_send, PWAIT, "kbdsend", 0);
				if (res != 0)
					return res;
			}
	} else if (!ioc_irq_status(IOC_IRQ_STX)) {
		if (sc->sc_cmdqueued)
			panic("%s: queue overflow", device_xname(sc->sc_dev));
		else {
			sc->sc_cmdqueue = data;
			sc->sc_statequeue = newstate;
			sc->sc_cmdqueued = 1;
			return 0;
		}
	}
	bus_space_write_1(bst, bsh, 0, data);
	sc->sc_state = newstate;
#ifdef ARCKBD_DEBUG
	log(LOG_DEBUG, "%s: sent 0x%02x.  now in state %s\n",
	    device_xname(sc->sc_dev), data, arckbd_statenames[newstate]);
#endif
	wakeup(&sc->sc_state);
	splx(s);
	if ((sc->sc_flags & AKF_POLLING) == 0)
		irq_enable(sc->sc_xirq);
	return 0;
}

void
elansc_setperf(int level)
{
	uint32_t eflags;
	uint8_t cpuctl, speed;

	level = (level > 50) ? 100 : 0;

	cpuctl = bus_space_read_1(elansc->sc_memt, elansc->sc_memh,
	    MMCR_CPUCTL);
	speed = (level == 100) ? 2 : 1;
	if ((cpuctl & CPUCTL_CPU_CLK_SPD_MASK) == speed)
		return;

	eflags = read_eflags();
	disable_intr();
	bus_space_write_1(elansc->sc_memt, elansc->sc_memh, MMCR_CPUCTL,
	    (cpuctl & ~CPUCTL_CPU_CLK_SPD_MASK) | speed);
	enable_intr();
	write_eflags(eflags);

	elansc_update_cpuspeed();
}