/*!
 *  ======== InterruptM3_intClear ========
 *  Clear interrupt and return payload
 */
UInt InterruptM3_intClear()
{
    UInt arg = InterruptM3_INVALIDPAYLOAD;

    /* First check whether incoming mailbox has a message */
    if (Core_getId() == 0) {
        /* If FIFO is empty, return InterruptM3_INVALIDPAYLOAD */
        if (REG32(MAILBOX_STATUS(SYSM3_MBX)) == 0) {
            return (arg);
        }
        else {
            /* If there is a message, return the argument to the caller */
            arg = REG32(MAILBOX_MESSAGE(SYSM3_MBX));
            REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(SYSM3_MBX);
        }
    }
    else {
        /* Clear the inter-M3 interrupt if necessary */
        if ((REG16(INTERRUPT_CORE_1) & 0x1) == 0x1) {
            REG16(INTERRUPT_CORE_1) &= ~(0x1);
        }

        /* If FIFO is empty, return InterruptM3_INVALIDPAYLOAD */
        if (REG32(MAILBOX_STATUS(APPM3_MBX)) == 0) {
            return (arg);
        }
        else {
            /* If there is a message, return the argument to the caller */
            arg = REG32(MAILBOX_MESSAGE(APPM3_MBX));
            REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(APPM3_MBX);

            if (REG32(MAILBOX_STATUS(APPM3_MBX)) != 0) {
                /* Trigger our own interrupt since another interrupt pending */
                REG16(INTERRUPT_CORE_1) |= 0x1;
            }
        }
    }

    return (arg);
}

void platform_init_timer(void)
{
	/* GPT2 */
	RMWREG32(CM_CLKSEL_PER, 0, 1, 1);
	RMWREG32(CM_ICLKEN_PER, 3, 1, 1);
	RMWREG32(CM_FCLKEN_PER, 3, 1, 1);

	// reset the GP timer 
	TIMER_REG(TIOCP_CFG) = 0x2;
	while ((TIMER_REG(TISTAT) & 1) == 0)
		;

	// set GPT2-9 clock inputs over to 32k
	*REG32(CM_CLKSEL_PER) = 0;

	// disable ints
	TIMER_REG(TIER) = 0;
	TIMER_REG(TISR) = 0x7; // clear any pending bits

	// XXX make sure 32K timer is running

	register_int_handler(GPT2_IRQ, &os_timer_tick, NULL);
}

/*!
 *  ======== InterruptDsp_intSend ========
 *  Send interrupt to the remote processor
 */
Void InterruptDsp_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo,
                          UArg arg)
{
    UInt key;
    
    /* 
     *  Before writing to a mailbox, check whehter it already contains a message
     *  If so, then don't write to the mailbox since we want one and only one
     *  message per interrupt.  Disable interrupts between reading 
     *  the MSGSTATUS_X register and writing to the mailbox to protect from 
     *  another thread doing an intSend at the same time
     *
     *  Note regarding possible race condition between local 'intSend' and 
     *  remote 'intClear':
     *  It is possible that we we read the MAILBOX_MSGSTATUS_X register during
     *  the remote side's intClear.  Therefore, we might choose _not_ to send
     *  write to the mailbox even though the mailbox is about to be cleared a
     *  few cycles later. In this case, the interrupt will be lost.
     *  This is OK, however. intClear should always be called by the Notify
     *  driver _before_ shared memory is read, so the event will be picked up
     *  anyway by the previous interrupt that caused intClear to be called.
     */
    if (remoteProcId == InterruptDsp_hostProcId) {
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(DSP_TO_HOST)) == 0) {
            REG32(MAILBOX_MESSAGE(DSP_TO_HOST)) = arg;
        }
        Hwi_restore(key);
    }
    else if (remoteProcId == InterruptDsp_videoProcId) {
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(DSP_TO_VIDEO)) == 0) {
            REG32(MAILBOX_MESSAGE(DSP_TO_VIDEO)) = arg;
        }
        Hwi_restore(key);
    }
    else { /* VPSS-M3 */
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(DSP_TO_VPSS)) == 0) {
            REG32(MAILBOX_MESSAGE(DSP_TO_VPSS)) = arg;
        }
        Hwi_restore(key);
    }
}

/* STATIC VARIABLE DECLARATIONS
 */
static HEADER * frhd; /* free list head */
static UINT32   memleft; /* memory left */
void console_init(void)
{

	int i;
	unsigned long dl;
	unsigned long dll;     
	unsigned long dlm;       
           
  	REG32( UART_LCR)=0x03000000;		//Line Control Register  8,n,1
  		
  	REG32( UART_FCR)=0xc7000000;		//FIFO Ccontrol Register
  	REG32( UART_IER)=0x00000000;
  	dl = (200000000 /16)/38400-1;
  	*(volatile unsigned long *)(0xa1000000) = dl ; 
  	dll = dl & 0xff;
  	dlm = dl / 0x100;
  	REG32( UART_LCR)=0x83000000;		//Divisor latch access bit=1
  	REG32( UART_DLL)=dll*0x1000000;
   	REG32( UART_DLM)=dlm*0x1000000; 
   	REG32( UART_LCR)=0x83000000& 0x7fffffff;	//Divisor latch access bit=0

}

/*!
 *  ======== InterruptDsp_intClear ========
 *  Clear interrupt 
 */
UInt InterruptDsp_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;
    
    if (remoteProcId == InterruptDsp_hostProcId) {
        arg = REG32(MAILBOX_MESSAGE(HOST_TO_DSP));  
        REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(HOST_TO_DSP);
    }
    else if (remoteProcId == InterruptDsp_videoProcId) {
        arg = REG32(MAILBOX_MESSAGE(VIDEO_TO_DSP));  
        REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(VIDEO_TO_DSP);
    }
    else { /* VPSS-M3 */
        arg = REG32(MAILBOX_MESSAGE(VPSS_TO_DSP));  
        REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(VPSS_TO_DSP);
    }
    
    /* Write to EOI (End Of Interrupt) register */
    REG32(MAILBOX_EOI_REG) = 0x1;

    return (arg);
}

int dvrmain(void)
{
	int r;
	unsigned short cpu_id;
	char commandline[MAX_COMMANDLINE_LENGTH];

	init_printf(NULL, _putc);
	init_commands();

	printf("\n");
	info(0, NULL);

	/* check CPU ID */
	cpu_id = REG32(RTGALAXY_SB2_CHIP_ID) & 0xffff;
	if (cpu_id != RTGALAXY_MARS) {
		printf("Wrong CPU ID detected (%04X) - aborting\n", cpu_id);
		return -1;
	}

	for (;;) {
		printf("rtdsr> ");

		r = get_command(commandline, MAX_COMMANDLINE_LENGTH, -1);

		if (r > 0) {
			if ((r = parse_command(commandline)) < 0 ) {
				if (r == PROGRAM_EXIT) {
					return 0;
				}
				printf("error %d executing command\n", r);
			}
		}
	}

	return 0;
}

//void __init bsp_timer_init(void)
void __init plat_time_init(void)
{
	unsigned int ocp;
	unsigned int cpu_freq_sel;
	
	/* set cp0_compare_irq and cp0_perfcount_irq */
#if 0
	cp0_compare_irq = BSP_COMPARE_IRQ; //mark_bb , wana rm !!
	cp0_perfcount_irq = BSP_PERFCOUNT_IRQ;

	if (cp0_perfcount_irq == cp0_compare_irq)
		cp0_perfcount_irq = -1;
#endif
	//write_c0_count(0); //mark_bb

//	mips_hpt_frequency = BSP_CPU0_FREQ / 2;
	cpu_freq_sel=GET_BITVAL(REG32(SYS_HW_STRAP), ST_CPU_FREQ_SEL_OFFSET, RANG4);
	ocp=cpu_clksel_table[cpu_freq_sel] * 1000000;
	mips_hpt_frequency = ocp / 2;

	write_c0_count(0); //need 
	//mips_clockevent_init(cp0_compare_irq);  // mark_bb , no need
	//mips_clocksource_init();
}

/**
 * ipc_write: ISH -> Host Communication
 *
 * 1. ISH FW ensures ISH2HOST doorbell busy bit [31] is cleared.
 * 2. ISH FW writes data (upto 128 bytes) to ISH2HOST message registers.
 * 3. ISH FW writes to ISH2HOST doorbell, busy bit (31) is set.
 * 4. Host SW receives interrupt, reads host PISR[0] to realize event.
 * 5. Upon reading data, Host driver clears ISH2HOST doorbell busy bit. This
 *    de-asserts the interrupt.
 * 6. ISH FW also receieves an interrupt for the clear event.
 */
static int ipc_write(uint8_t peer_id, void *buff, uint32_t buff_size)
{
	struct ipc_if_ctx *ctx;
	uint32_t drbl_val = 0;
#ifdef ISH_DEBUG
	int i;
#endif

	ctx = &ipc_peer_ctxs[peer_id];

	if (ipc_wait_until_msg_consumed(ctx, IPC_TIMEOUT)) {
		/* timeout */
		return IPC_FAILURE;
	}
#ifdef ISH_DEBUG
	CPRINTF("ipc_write, len=0x%0x [", buff_size);
	for (i = 0; i < buff_size; i++)
		CPRINTF("0x%0x ", (uint8_t) ((char *)buff)[i]);
	CPUTS("]\n");
#endif

	/* write message */
	if (buff_size <= IPC_MSG_MAX_SIZE) {
		/* write to message register */
		memcpy((uint32_t *) ctx->out_msg_reg, buff, buff_size);
		drbl_val = IPC_BUILD_HEADER(buff_size, IPC_PROTOCOL_ECP,
					    SET_BUSY);
	} else {
		return IPC_FAILURE;
	}

	/* write doorbell */
	REG32(ctx->out_drbl_reg) = drbl_val;

	return EC_SUCCESS;
}

void
nxc2600_aic_set_dma_mode_rx_packet(struct nxc2600_dma_mode *dma_mode)
{
        switch(REG32(NXC2600_AIC_CR2)&NXC2600_AIC_CR2_IASS_MASK)
        {
                case NXC2600_AIC_CR2_IASS_8_BIT:
                        dma_mode->mode |= NXC2600_DMA_DCS_TSZ_8_BIT |
                                          NXC2600_DMA_DCS_DP_8_BIT |
                                          NXC2600_DMA_DCS_SP_8_BIT;

                        break;
                case NXC2600_AIC_CR2_IASS_16_BIT:
                        dma_mode->mode |= NXC2600_DMA_DCS_TSZ_16_BIT |
                                          NXC2600_DMA_DCS_DP_16_BIT |
                                          NXC2600_DMA_DCS_SP_16_BIT;
                        break;
                case NXC2600_AIC_CR2_IASS_18_BIT:
                case NXC2600_AIC_CR2_IASS_20_BIT:
                        dma_mode->mode |= NXC2600_DMA_DCS_TSZ_32_BIT |
                                          NXC2600_DMA_DCS_DP_32_BIT |
                                          NXC2600_DMA_DCS_SP_32_BIT;
                        break;
        }
}

void audio_AGC_DMA_Isr(void)
{
	u32 agc_sta = rd_reg(AGC_STA);
	//deg_Printf(" %x\n",agc_sta);
	if((agc_sta & 0x1) == 0x1)
		wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(0));

	wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)&(~BIT(5)));
	if((g_stcJpegInfo.iAudioFillBufCnt+1) < (g_stcJpegInfo.iAudioFSWriteBufCnt + AUDIO_BUFFER_NUM))
	{
		if(audio_buffer_ptr == ((u32)JPEG_BUFFER_END_ADDRESS - 0x2000))
			audio_buffer_ptr = (u32)JPEG_BUFFER_END_ADDRESS-(AUDIO_BUFFER_NUM*0x2000);
		else
			audio_buffer_ptr += g_stcJpegInfo.dwAudiobufSize;

		g_stcJpegInfo.iAudioFillBufCnt++;
	}
	else
	{
		deg_Printf("d");
		g_stcJpegInfo.i30FrameCnt -=((192*(u32Framecount+1))/25 -(192*u32Framecount)/25);
		u32Framecount++;
		if(u32Framecount >= 25)
		{
			u32Framecount = 0;
		}
		g_stcJpegInfo.iJpeg10MSCnt -= 25;
	}
	dmac_channel_disable(AUDIO_ADC_DMA_CH);
	//dma_peri2mem_Ext(AUDIO_ADC_DMA_CH, (0<<11)|(6<<7)|(0<<1), (0<<11)|(0<<10), AUADC_DMA_TX_ADR, (audio_buffer_ptr+8), (2048-2));
	REG32(DMA_DAR0L + AUDIO_ADC_DMA_CH*0x58) = (u32)(audio_buffer_ptr+8);
	dmac_channel_enable(AUDIO_ADC_DMA_CH);
	
	wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)|(BIT(5)));
	wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(5));
}

/*
 *  ======== InterruptEve_intPost ========
 *  Simulate an interrupt from a remote processor
 */
Void InterruptEve_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo,
                            UArg arg)
{
    UInt key;

    if (srcProcId == InterruptEve_hostProcId) {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(HOST_TO_EVE)) == 0) {
            /* write the mailbox message to arp32 */
            REG32(MAILBOX_MESSAGE(HOST_TO_EVE)) = arg;
        }

        /* restore interrupts */
        Hwi_restore(key);
    }
    else if ((srcProcId == InterruptEve_videoProcId) ||
        (srcProcId == InterruptEve_vpssProcId)) {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(VIDEO_TO_EVE)) == 0) {
            /* write the mailbox message to arp32 */
            REG32(MAILBOX_MESSAGE(VIDEO_TO_EVE)) = arg;
        }

        /* restore interrupts */
        Hwi_restore(key);
    }
    else {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(DSP_TO_EVE)) == 0) {
            /* write the mailbox message to arp32 */
            REG32(MAILBOX_MESSAGE(DSP_TO_EVE)) = arg;
        }

        /* restore interrupts */
        Hwi_restore(key);
    }
}

/*
 *  ======== InterruptEve_intSend ========
 *  Send interrupt to the remote processor
 */
Void InterruptEve_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo,
                          UArg arg)
{
    UInt key;

    if (remoteProcId == InterruptEve_hostProcId) {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(EVE_TO_HOST)) == 0) {
            /* write the mailbox message to host */
            REG32(MAILBOX_MESSAGE(EVE_TO_HOST)) = arg;
        }

        /* restore interrupts */
        Hwi_restore(key);
    }
    else if ((remoteProcId == InterruptEve_videoProcId) ||
        (remoteProcId == InterruptEve_vpssProcId)) {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(EVE_TO_VIDEO)) == 0) {
            /* write the mailbox message to video-m3 */
            REG32(MAILBOX_MESSAGE(EVE_TO_VIDEO)) = arg;
        }

        /* restore interrupts */
        Hwi_restore(key);
    }
    else {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(EVE_TO_DSP)) == 0) {
            /* write the mailbox message to dsp */
            REG32(MAILBOX_MESSAGE(EVE_TO_DSP)) = arg;
        }

        /* restore interrupts */
        key = Hwi_disable();
    }
}

static void I486OP(cpuid)(void)				/* Opcode 0x0F A2 */
{
	switch (REG32(EAX))
	{
		case 0:
		{
			REG32(EAX) = I.cpuid_max_input_value_eax;
			REG32(EBX) = I.cpuid_id0;
			REG32(ECX) = I.cpuid_id2;
			REG32(EDX) = I.cpuid_id1;
			CYCLES(CYCLES_CPUID);
			break;
		}

		case 1:
		{
			REG32(EAX) = I.cpu_version;
			REG32(EDX) = I.feature_flags;
			CYCLES(CYCLES_CPUID_EAX1);
			break;
		}
	}
}

/*
 *  ======== InterruptEve_intClear ========
 *  Clear interrupt
 */
UInt InterruptEve_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;

    if (remoteProcId == InterruptEve_hostProcId) { /* HOST */
        arg = REG32(MAILBOX_MESSAGE(HOST_TO_EVE));
        REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(HOST_TO_EVE);
    }
    else if ((remoteProcId == InterruptEve_videoProcId) || /* VIDEO-M3 */
        (remoteProcId == InterruptEve_vpssProcId)) {
        arg = REG32(MAILBOX_MESSAGE(VIDEO_TO_EVE));
        REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(VIDEO_TO_EVE);
    }
    else { /* DSP */
        arg = REG32(MAILBOX_MESSAGE(DSP_TO_EVE));
        REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(DSP_TO_EVE);
    }

    /* Write to EOI (End Of Interrupt) register */
    REG32(MAILBOX_EOI_REG) = 0x1;

    return (arg);
}

static void  unmask_irq(unsigned int irq)
{
#ifdef CONFIG_RTL_EB8186
    outl((inl(GIMR0) | (1 << irq)),GIMR0);
    inl(GIMR0);
#endif

#ifdef CONFIG_RTL865X
#ifdef CONFIG_RTK_VOIP
    if (irq == 6) // PCM
        REG32(GIMR) = (REG32(GIMR)) | (1 << (25-irq));
    else
#endif
        REG32(GIMR) = (REG32(GIMR)) | (1 << (17-irq));
    if ( (irq == 0) || (irq == 1) || (irq == 6) )
        REG32(IRR2)|= ((irqRoute[irq].idx & 0xF)<<irqRoute[irq].base);
    else
        REG32(IRR1)|= ((irqRoute[irq].idx & 0xF)<<irqRoute[irq].base);
#endif
}

/* Illegal instruction test */
int illegal_insn_test (void)
{
  int ret;

  /* Reset except counter */
  except_count = 0;
  except_mask = 0;
  except_pc = 0;
  except_ea = 0;

  /* Set illegal insn code.

     Original code had two bugs. First it jumped to the illegal instruction,
     rather than the immediately preceding l.jr r9 (allowing us to
     recover). Secondly it used 0xffffffff as an illegal instruction. Except
     it isn't - it's l.cust8 0x3ffffff.

     Fixed by a) jumping to the correct location and b) really using an
     illegal instruction (opcode 0x3a. */
#ifndef __OR1K_NODELAY__
  REG32(RAM_START + (RAM_SIZE/2)) = REG32((unsigned long)jump_back + 4);
  REG32(RAM_START + (RAM_SIZE/2) + 4) = 0xe8000000;

  /* Check if there was illegal insn exception. Note that if an illegal
     instruction occurs in a delay slot (like this one), then the exception
     PC is the address of the jump instruction. */
#else
  REG32(RAM_START + (RAM_SIZE/2)) = 0xe8000000;
  REG32(RAM_START + (RAM_SIZE/2) + 4) = REG32((unsigned long)jump_back + 8);
#endif

  ret = call (RAM_START + (RAM_SIZE/2), 0 );	/* JPB */
  (void) ret; /* suppress unused variable warning */

  ASSERT(except_count == 1);
  ASSERT(except_mask == (1 << V_ILLINSN));
  ASSERT(except_pc == (RAM_START + (RAM_SIZE/2)));

  return 0;
}

void dac_init()                                                          
{
//	Uart_SendByte ('\n');Uart_SendByte ('e');Uart_SendByte ('\n');	
	
	REG32(PCON0)   &= ~(1<<21);    // enable dac clock
	REG32(CLKCON0) &= ~(BIT(6)|BIT(7)); 
	REG32(CLKCON1) &= ~(0xf<<8);
	REG32(CLKCON1) |= (9<<8);//10 div  240M/(9+1)=24M
	
	obuf_cfg();
	
	REG32(DAC_ACON0) |= BIT(2);
	wr_reg(FIFO_CNT, DAC_BLOCK_CNT);//
//	wr_reg(OBUF_CLR, 0x02);//clear pending
	
//	dac_analog_init();
	
#if 0
	if(adc_single_double_ch)
	{
		music_llp0.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (1<<4) | (1<<1);
		music_llp1.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (1<<4) | (1<<1);
	}
	else
	{
		music_llp0.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (2<<4) | (2<<1);
		music_llp1.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (2<<4) | (2<<1);
	}
#endif
	
	llp_peri2mem (AUDIO_DAC_DMA_CH, (0<<7)|(7<<11), 0, &adc_dac0); 
	
	wr_reg(DACCFG, (rd_reg(DACCFG)& 0xffffff0f) | ((DAC_SAMPLE_32000)<<4) | DAC_EN);

	digital_volume_set(0x3fff,1,0);//

	REG32(DAC_ACON0) &= ~BIT(2);
	deg_Printf("dac_init\r\n");
	return;
}

LOCAL BOOLEAN __is_rw_ok(uint32 addr,uint32 val)
{
    volatile uint32 i;
    BOOLEAN ret = SCI_TRUE;

    REG32(addr) = 0;
    REG32(addr) 	= val;

    REG32(addr + 4) = 0;
    REG32(addr + 4) = (~val);

    delay(100);

    if ((REG32(addr) == val) && (REG32(addr + 4) == (~val)))
    {
        ret = SCI_TRUE;
    }
    else
    {
        ret = SCI_FALSE;
    }

    return ret;
}

static inline Void IpcPower_setWugen()
{
    REG32(WUGEN_MEVT1) |= WUGEN_INT_MASK;
}

void inline bsp_timer_ack(void)
{
    REG32(BSP_TCIR) |= BSP_TC0IP;
}