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C++ REGFLAG_R函数代码示例

原作者: [db:作者] 来自: [db:来源] 收藏 邀请

本文整理汇总了C++中REGFLAG_R函数的典型用法代码示例。如果您正苦于以下问题：C++ REGFLAG_R函数的具体用法？C++ REGFLAG_R怎么用？C++ REGFLAG_R使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。



在下文中一共展示了REGFLAG_R函数的16个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的C++代码示例。

示例1: switch

bool mips3_frontend::describe_cop2(UINT32 op, opcode_desc &desc)
{
	// any COP2 instruction can potentially cause an exception
	desc.flags |= OPFLAG_CAN_CAUSE_EXCEPTION;

	switch (RSREG)
	{
		case 0x00:  // MFCz
		case 0x01:  // DMFCz
		case 0x02:  // CFCz
			desc.regout[0] |= REGFLAG_R(RTREG);
			return true;

		case 0x04:  // MTCz
		case 0x05:  // DMTCz
		case 0x06:  // CTCz
			desc.regin[0] |= REGFLAG_R(RTREG);
			return true;

		case 0x08:  // BC
			switch (RTREG)
			{
				case 0x00:  // BCzF
				case 0x01:  // BCzT
					desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
					desc.targetpc = desc.pc + 4 + (SIMMVAL << 2);
					desc.delayslots = 1;
					return true;
			}
			return false;
	}

	return false;
}
开发者ID:dezi，项目名称:mame-libretro-odroid，代码行数:34，代码来源:mips3fe.c


示例2: describe_instruction_cop2

static int describe_instruction_cop2(mips3_state *mipsaa, UINT32 op, opcode_desc *desc)
{
	/* any COP2 instruction can potentially cause an exception */
	desc->flags |= OPFLAG_CAN_CAUSE_EXCEPTION;

	switch (RSREG)
	{
		case 0x00:	/* MFCz */
		case 0x01:	/* DMFCz */
		case 0x02:	/* CFCz */
			desc->regout[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x04:	/* MTCz */
		case 0x05:	/* DMTCz */
		case 0x06:	/* CTCz */
			desc->regin[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x08:	/* BC */
			switch (RTREG)
			{
				case 0x00:	/* BCzF */
				case 0x01:	/* BCzT */
					desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
					desc->targetpc = desc->pc + 4 + (SIMMVAL << 2);
					desc->delayslots = 1;
					return TRUE;
			}
			return FALSE;
	}

	return FALSE;
}
开发者ID:DarrenBranford，项目名称:MAME4iOS，代码行数:34，代码来源:mips3fe.c


示例3: describe_instruction_regimm

static int describe_instruction_regimm(mips3_state *mipsaa, UINT32 op, opcode_desc *desc)
{
	switch (RTREG)
	{
		case 0x00:	/* BLTZ */
		case 0x01:	/* BGEZ */
		case 0x02:	/* BLTZL */
		case 0x03:	/* BGEZL */
			if (RTREG == 0x01 && RSREG == 0)
				desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			else
			{
				desc->regin[0] |= REGFLAG_R(RSREG);
				desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
			}
			desc->targetpc = desc->pc + 4 + (SIMMVAL << 2);
			desc->delayslots = 1;
			desc->skipslots = (RTREG & 0x02) ? 1 : 0;
			return TRUE;

		case 0x08:	/* TGEI */
		case 0x09:	/* TGEIU */
		case 0x0a:	/* TLTI */
		case 0x0b:	/* TLTIU */
		case 0x0c:	/* TEQI */
		case 0x0e:	/* TNEI */
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->flags |= OPFLAG_CAN_CAUSE_EXCEPTION;
			return TRUE;

		case 0x10:	/* BLTZAL */
		case 0x11:	/* BGEZAL */
		case 0x12:	/* BLTZALL */
		case 0x13:	/* BGEZALL */
			if (RTREG == 0x11 && RSREG == 0)
				desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			else
			{
				desc->regin[0] |= REGFLAG_R(RSREG);
				desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
			}
			desc->regout[0] |= REGFLAG_R(31);
			desc->targetpc = desc->pc + 4 + (SIMMVAL << 2);
			desc->delayslots = 1;
			desc->skipslots = (RTREG & 0x02) ? 1 : 0;
			return TRUE;
	}

	return FALSE;
}
开发者ID:DarrenBranford，项目名称:MAME4iOS，代码行数:50，代码来源:mips3fe.c


示例4: describe_instruction_cop0

static int describe_instruction_cop0(rsp_state *rsp, UINT32 op, opcode_desc *desc)
{
	switch (RSREG)
	{
		case 0x00:	/* MFCz */
			desc->regout[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x04:	/* MTCz */
			desc->regin[0] |= REGFLAG_R(RTREG);
			return TRUE;
	}

	return FALSE;
}
开发者ID:AltimorTASDK，项目名称:shmupmametgm，代码行数:15，代码来源:rspfe.c


示例5: switch

bool rsp_frontend::describe_cop2(UINT32 op, opcode_desc &desc)
{
	switch (RSREG)
	{
		case 0x00:  // MFCz
		case 0x02:  // CFCz
			desc.regout[0] |= REGFLAG_R(RTREG);
			return true;

		case 0x04:  // MTCz
		case 0x06:  // CTCz
			desc.regin[0] |= REGFLAG_R(RTREG);
			return true;
	}

	return false;
}
开发者ID:BrandoCommando，项目名称:mame，代码行数:17，代码来源:rspfe.c


示例6: describe_instruction_idt

static int describe_instruction_idt(mips3_state *mips, UINT32 op, opcode_desc *desc)
{
	switch (op & 0x1f)
	{
		case 0: /* MAD */
		case 1: /* MADU */
			desc->gpr.used |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG) | REGFLAG_LO | REGFLAG_HI;
			desc->gpr.modified |= REGFLAG_LO | REGFLAG_HI;
			return TRUE;

		case 2: /* MUL */
			desc->gpr.used |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
			desc->gpr.modified |= REGFLAG_R(RDREG);
			desc->cycles = 3;
			return TRUE;
	}

	return FALSE;
}
开发者ID:broftkd，项目名称:historic-mame，代码行数:19，代码来源:mips3fe.c


示例7: describe_instruction_idt

static int describe_instruction_idt(mips3_state *mipsaa, UINT32 op, opcode_desc *desc)
{
	/* only on the R4650 */
	if (mipsaa->flavor != MIPS3_TYPE_R4650)
		return FALSE;

	switch (op & 0x1f)
	{
		case 0: /* MAD */
		case 1: /* MADU */
			desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
			desc->regin[2] |= REGFLAG_LO | REGFLAG_HI;
			desc->regout[2] |= REGFLAG_LO | REGFLAG_HI;
			return TRUE;

		case 2: /* MUL */
			desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
			desc->regout[0] |= REGFLAG_R(RDREG);
			desc->cycles = 3;
			return TRUE;
	}

	return FALSE;
}
开发者ID:DarrenBranford，项目名称:MAME4iOS，代码行数:24，代码来源:mips3fe.c


示例8: describe_instruction_cop1x

static int describe_instruction_cop1x(mips3_state *mipsaa, UINT32 op, opcode_desc *desc)
{
	/* any COP1 instruction can potentially cause an exception */
//  desc->flags |= OPFLAG_CAN_CAUSE_EXCEPTION;

	switch (op & 0x3f)
	{
		case 0x00:	/* LWXC1 */
		case 0x01:	/* LDXC1 */
			desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
			desc->regout[1] |= REGFLAG_CPR1(FDREG);
			desc->flags |= OPFLAG_READS_MEMORY;
			return TRUE;

		case 0x08:	/* SWXC1 */
		case 0x09:	/* SDXC1 */
			desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
			desc->regin[1] |= REGFLAG_CPR1(FDREG);
			desc->flags |= OPFLAG_WRITES_MEMORY;
			return TRUE;

		case 0x0f:	/* PREFX */
			/* effective no-op */
			return TRUE;

		case 0x20:	case 0x21:	/* MADD */
		case 0x28:	case 0x29:	/* MSUB */
		case 0x30:	case 0x31:	/* NMADD */
		case 0x38:	case 0x39:	/* NMSUB */
			desc->regin[1] |= REGFLAG_CPR1(FSREG) | REGFLAG_CPR1(FTREG) | REGFLAG_CPR1(FRREG);
			desc->regout[1] |= REGFLAG_CPR1(FDREG);
			return TRUE;
	}

	return FALSE;
}
开发者ID:DarrenBranford，项目名称:MAME4iOS，代码行数:36，代码来源:mips3fe.c


示例9: describe_instruction_regimm

static int describe_instruction_regimm(rsp_state *rsp, UINT32 op, opcode_desc *desc)
{
	switch (RTREG)
	{
		case 0x00:	/* BLTZ */
		case 0x01:	/* BGEZ */
			if (RTREG == 0x01 && RSREG == 0)
				desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			else
			{
				desc->regin[0] |= REGFLAG_R(RSREG);
				desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
			}
			desc->targetpc = ((desc->pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
			desc->delayslots = 1;
			desc->skipslots = (RTREG & 0x02) ? 1 : 0;
			return TRUE;

		case 0x10:	/* BLTZAL */
		case 0x11:	/* BGEZAL */
			if (RTREG == 0x11 && RSREG == 0)
				desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			else
			{
				desc->regin[0] |= REGFLAG_R(RSREG);
				desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
			}
			desc->regout[0] |= REGFLAG_R(31);
			desc->targetpc = ((desc->pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
			desc->delayslots = 1;
			desc->skipslots = (RTREG & 0x02) ? 1 : 0;
			return TRUE;
	}

	return FALSE;
}
开发者ID:AltimorTASDK，项目名称:shmupmametgm，代码行数:36，代码来源:rspfe.c


示例10: describe_instruction_special

static int describe_instruction_special(rsp_state *rsp, UINT32 op, opcode_desc *desc)
{
	switch (op & 63)
	{
		case 0x00:	/* SLL */
		case 0x02:	/* SRL */
		case 0x03:	/* SRA */
			desc->regin[0] |= REGFLAG_R(RTREG);
			desc->regout[0] |= REGFLAG_R(RDREG);
			return TRUE;

		case 0x04:	/* SLLV */
		case 0x06:	/* SRLV */
		case 0x07:	/* SRAV */
		case 0x21:	/* ADDU */
		case 0x23:	/* SUBU */
		case 0x24:	/* AND */
		case 0x25:	/* OR */
		case 0x26:	/* XOR */
		case 0x27:	/* NOR */
		case 0x2a:	/* SLT */
		case 0x2b:	/* SLTU */
			desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
			desc->regout[0] |= REGFLAG_R(RDREG);
			return TRUE;

		case 0x20:	/* ADD */
		case 0x22:	/* SUB */
			desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
			desc->regout[0] |= REGFLAG_R(RDREG);
			return TRUE;

		case 0x08:	/* JR */
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			desc->targetpc = BRANCH_TARGET_DYNAMIC;
			desc->delayslots = 1;
			return TRUE;

		case 0x09:	/* JALR */
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->regout[0] |= REGFLAG_R(RDREG);
			desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			desc->targetpc = BRANCH_TARGET_DYNAMIC;
			desc->delayslots = 1;
			return TRUE;

		case 0x0d:	/* BREAK */
			desc->flags |= OPFLAG_END_SEQUENCE;
			desc->targetpc = BRANCH_TARGET_DYNAMIC;
			return TRUE;
	}

	return FALSE;
}
开发者ID:AltimorTASDK，项目名称:shmupmametgm，代码行数:55，代码来源:rspfe.c


示例11: describe_instruction_special

static int describe_instruction_special(mips3_state *mipsaa, UINT32 op, opcode_desc *desc)
{
	switch (op & 63)
	{
		case 0x00:	/* SLL */
		case 0x02:	/* SRL */
		case 0x03:	/* SRA */
		case 0x38:	/* DSLL */
		case 0x3a:	/* DSRL */
		case 0x3b:	/* DSRA */
		case 0x3c:	/* DSLL32 */
		case 0x3e:	/* DSRL32 */
		case 0x3f:	/* DSRA32 */
			desc->regin[0] |= REGFLAG_R(RTREG);
			desc->regout[0] |= REGFLAG_R(RDREG);
			return TRUE;

		case 0x0a:	/* MOVZ - MIPS IV */
		case 0x0b:	/* MOVN - MIPS IV */
			if (mipsaa->flavor < MIPS3_TYPE_MIPS_IV)
				return FALSE;
			desc->regin[0] |= REGFLAG_R(RDREG);
		case 0x04:	/* SLLV */
		case 0x06:	/* SRLV */
		case 0x07:	/* SRAV */
		case 0x14:	/* DSLLV */
		case 0x16:	/* DSRLV */
		case 0x17:	/* DSRAV */
		case 0x21:	/* ADDU */
		case 0x23:	/* SUBU */
		case 0x24:	/* AND */
		case 0x25:	/* OR */
		case 0x26:	/* XOR */
		case 0x27:	/* NOR */
		case 0x2a:	/* SLT */
		case 0x2b:	/* SLTU */
		case 0x2d:	/* DADDU */
		case 0x2f:	/* DSUBU */
			desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
			desc->regout[0] |= REGFLAG_R(RDREG);
			return TRUE;

		case 0x20:	/* ADD */
		case 0x22:	/* SUB */
		case 0x2c:	/* DADD */
		case 0x2e:	/* DSUB */
			desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
			desc->regout[0] |= REGFLAG_R(RDREG);
			desc->flags |= OPFLAG_CAN_CAUSE_EXCEPTION;
			return TRUE;

		case 0x30:	/* TGE */
		case 0x31:	/* TGEU */
		case 0x32:	/* TLT */
		case 0x33:	/* TLTU */
		case 0x34:	/* TEQ */
		case 0x36:	/* TNE */
			desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
			desc->flags |= OPFLAG_CAN_CAUSE_EXCEPTION;
			return TRUE;

		case 0x01:	/* MOVF - MIPS IV */
			if (mipsaa->flavor < MIPS3_TYPE_MIPS_IV)
				return FALSE;
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->regin[2] |= REGFLAG_FCC;
			desc->regout[0] |= REGFLAG_R(RDREG);
			return TRUE;

		case 0x08:	/* JR */
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			desc->targetpc = BRANCH_TARGET_DYNAMIC;
			desc->delayslots = 1;
			return TRUE;

		case 0x09:	/* JALR */
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->regout[0] |= REGFLAG_R(RDREG);
			desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			desc->targetpc = BRANCH_TARGET_DYNAMIC;
			desc->delayslots = 1;
			return TRUE;

		case 0x10:	/* MFHI */
			desc->regin[0] |= REGFLAG_HI;
			desc->regout[0] |= REGFLAG_R(RDREG);
			return TRUE;

		case 0x11:	/* MTHI */
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->regout[0] |= REGFLAG_HI;
			return TRUE;

		case 0x12:	/* MFLO */
			desc->regin[2] |= REGFLAG_LO;
			desc->regout[0] |= REGFLAG_R(RDREG);
			return TRUE;

		case 0x13:	/* MTLO */
//.........这里部分代码省略.........
开发者ID:DarrenBranford，项目名称:MAME4iOS，代码行数:101，代码来源:mips3fe.c


示例12: mips3fe_describe

int mips3fe_describe(void *param, opcode_desc *desc, const opcode_desc *prev)
{
	mips3_state *mipsaa = (mips3_state *)param;
	UINT32 op, opswitch;

	/* compute the physical PC */
	if (!mips3com_translate_address(mipsaa, ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH, &desc->physpc))
	{
		/* uh-oh: a page fault; leave the description empty and just if this is the first instruction, leave it empty and */
		/* mark as needing to validate; otherwise, just end the sequence here */
		desc->flags |= OPFLAG_VALIDATE_TLB | OPFLAG_CAN_CAUSE_EXCEPTION | OPFLAG_COMPILER_PAGE_FAULT | OPFLAG_VIRTUAL_NOOP | OPFLAG_END_SEQUENCE;
		return TRUE;
	}

	/* fetch the opcode */
	op = desc->opptr.l[0] = memory_decrypted_read_dword(mipsaa->program, desc->physpc);

	/* all instructions are 4 bytes and default to a single cycle each */
	desc->length = 4;
	desc->cycles = 1;

	/* parse the instruction */
	opswitch = op >> 26;
	switch (opswitch)
	{
		case 0x00:	/* SPECIAL */
			return describe_instruction_special(mipsaa, op, desc);

		case 0x01:	/* REGIMM */
			return describe_instruction_regimm(mipsaa, op, desc);

		case 0x10:	/* COP0 */
			return describe_instruction_cop0(mipsaa, op, desc);

		case 0x11:	/* COP1 */
			return describe_instruction_cop1(mipsaa, op, desc);

		case 0x12:	/* COP2 */
			return describe_instruction_cop2(mipsaa, op, desc);

		case 0x13:	/* COP1X - MIPS IV */
			if (mipsaa->flavor < MIPS3_TYPE_MIPS_IV)
				return FALSE;
			return describe_instruction_cop1x(mipsaa, op, desc);

		case 0x1c:	/* IDT-specific opcodes: mad/madu/mul on R4640/4650, msub on RC32364 */
			return describe_instruction_idt(mipsaa, op, desc);

		case 0x02:	/* J */
			desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			desc->targetpc = (desc->pc & 0xf0000000) | (LIMMVAL << 2);
			desc->delayslots = 1;
			return TRUE;

		case 0x03:	/* JAL */
			desc->regout[0] |= REGFLAG_R(31);
			desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			desc->targetpc = (desc->pc & 0xf0000000) | (LIMMVAL << 2);
			desc->delayslots = 1;
			return TRUE;

		case 0x04:	/* BEQ */
		case 0x05:	/* BNE */
		case 0x14:	/* BEQL */
		case 0x15:	/* BNEL */
			if ((opswitch == 0x04 || opswitch == 0x14) && RSREG == RTREG)
				desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			else
			{
				desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
				desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
			}
			desc->targetpc = desc->pc + 4 + (SIMMVAL << 2);
			desc->delayslots = 1;
			desc->skipslots = (opswitch & 0x10) ? 1 : 0;
			return TRUE;

		case 0x06:	/* BLEZ */
		case 0x07:	/* BGTZ */
		case 0x16:	/* BLEZL */
		case 0x17:	/* BGTZL */
			if ((opswitch == 0x06 || opswitch == 0x16) && RSREG == 0)
				desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			else
			{
				desc->regin[0] |= REGFLAG_R(RSREG);
				desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
			}
			desc->targetpc = desc->pc + 4 + (SIMMVAL << 2);
			desc->delayslots = 1;
			desc->skipslots = (opswitch & 0x10) ? 1 : 0;
			return TRUE;

		case 0x08:	/* ADDI */
		case 0x18:	/* DADDI */
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->regout[0] |= REGFLAG_R(RTREG);
			desc->flags |= OPFLAG_CAN_CAUSE_EXCEPTION;
			return TRUE;

//.........这里部分代码省略.........
开发者ID:DarrenBranford，项目名称:MAME4iOS，代码行数:101，代码来源:mips3fe.c


示例13: describe_instruction_cop1

static int describe_instruction_cop1(mips3_state *mipsaa, UINT32 op, opcode_desc *desc)
{
	/* any COP1 instruction can potentially cause an exception */
//  desc->flags |= OPFLAG_CAN_CAUSE_EXCEPTION;

	switch (RSREG)
	{
		case 0x00:	/* MFCz */
		case 0x01:	/* DMFCz */
			desc->regin[1] |= REGFLAG_CPR1(RDREG);
			desc->regout[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x02:	/* CFCz */
			desc->regout[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x04:	/* MTCz */
		case 0x05:	/* DMTCz */
			desc->regin[0] |= REGFLAG_R(RTREG);
			desc->regout[1] |= REGFLAG_CPR1(RDREG);
			return TRUE;

		case 0x06:	/* CTCz */
			desc->regin[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x08:	/* BC */
			switch (RTREG & 3)
			{
				case 0x00:	/* BCzF */
				case 0x01:	/* BCzT */
				case 0x02:	/* BCzFL */
				case 0x03:	/* BCzTL */
					desc->regin[2] |= REGFLAG_FCC;
					desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
					desc->targetpc = desc->pc + 4 + (SIMMVAL << 2);
					desc->delayslots = 1;
					desc->skipslots = (RTREG & 0x02) ? 1 : 0;
					return TRUE;
			}
			return FALSE;

		case 0x10:	case 0x11:	case 0x12:	case 0x13:	case 0x14:	case 0x15:	case 0x16:	case 0x17:
		case 0x18:	case 0x19:	case 0x1a:	case 0x1b:	case 0x1c:	case 0x1d:	case 0x1e:	case 0x1f:	/* COP */
			switch (op & 0x3f)
			{
				case 0x12:	/* MOVZ - MIPS IV */
				case 0x13:	/* MOVN - MIPS IV */
					if (mipsaa->flavor < MIPS3_TYPE_MIPS_IV)
						return FALSE;
				case 0x00:	/* ADD */
				case 0x01:	/* SUB */
				case 0x02:	/* MUL */
				case 0x03:	/* DIV */
					desc->regin[1] |= REGFLAG_CPR1(FSREG) | REGFLAG_CPR1(FTREG);
					desc->regout[1] |= REGFLAG_CPR1(FDREG);
					return TRUE;

				case 0x15:	/* RECIP - MIPS IV */
				case 0x16:	/* RSQRT - MIPS IV */
					if (mipsaa->flavor < MIPS3_TYPE_MIPS_IV)
						return FALSE;
				case 0x04:	/* SQRT */
				case 0x05:	/* ABS */
				case 0x06:	/* MOV */
				case 0x07:	/* NEG */
				case 0x08:	/* ROUND.L */
				case 0x09:	/* TRUNC.L */
				case 0x0a:	/* CEIL.L */
				case 0x0b:	/* FLOOR.L */
				case 0x0c:	/* ROUND.W */
				case 0x0d:	/* TRUNC.W */
				case 0x0e:	/* CEIL.W */
				case 0x0f:	/* FLOOR.W */
				case 0x20:	/* CVT.S */
				case 0x21:	/* CVT.D */
				case 0x24:	/* CVT.W */
				case 0x25:	/* CVT.L */
					desc->regin[1] |= REGFLAG_CPR1(FSREG);
					desc->regout[1] |= REGFLAG_CPR1(FDREG);
					return TRUE;

				case 0x11:	/* MOVT/F - MIPS IV */
					if (mipsaa->flavor < MIPS3_TYPE_MIPS_IV)
						return FALSE;
					desc->regin[1] |= REGFLAG_CPR1(FSREG);
					desc->regin[2] |= REGFLAG_FCC;
					desc->regout[1] |= REGFLAG_CPR1(FDREG);
					return TRUE;

				case 0x30:	case 0x38:	/* C.F */
				case 0x31:	case 0x39:	/* C.UN */
					desc->regout[2] |= REGFLAG_FCC;
					return TRUE;

				case 0x32:	case 0x3a:	/* C.EQ */
				case 0x33:	case 0x3b:	/* C.UEQ */
				case 0x34:	case 0x3c:	/* C.OLT */
				case 0x35:	case 0x3d:	/* C.ULT */
//.........这里部分代码省略.........
开发者ID:DarrenBranford，项目名称:MAME4iOS，代码行数:101，代码来源:mips3fe.c


示例14: assert

bool mips3_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
{
	UINT32 op, opswitch;

	// compute the physical PC
	assert((desc.physpc & 3) == 0);
	if (!mips3com_translate_address(&m_context, AS_PROGRAM, TRANSLATE_FETCH, &desc.physpc))
	{
		// uh-oh: a page fault; leave the description empty and just if this is the first instruction, leave it empty and
		// mark as needing to validate; otherwise, just end the sequence here
		desc.flags |= OPFLAG_VALIDATE_TLB | OPFLAG_CAN_CAUSE_EXCEPTION | OPFLAG_COMPILER_PAGE_FAULT | OPFLAG_VIRTUAL_NOOP | OPFLAG_END_SEQUENCE;
		return true;
	}

	// fetch the opcode
	assert((desc.physpc & 3) == 0);
	op = desc.opptr.l[0] = m_context.direct->read_decrypted_dword(desc.physpc);

	// all instructions are 4 bytes and default to a single cycle each
	desc.length = 4;
	desc.cycles = 1;

	// parse the instruction
	opswitch = op >> 26;
	switch (opswitch)
	{
		case 0x00:  // SPECIAL
			return describe_special(op, desc);

		case 0x01:  // REGIMM
			return describe_regimm(op, desc);

		case 0x10:  // COP0
			return describe_cop0(op, desc);

		case 0x11:  // COP1
			return describe_cop1(op, desc);

		case 0x12:  // COP2
			return describe_cop2(op, desc);

		case 0x13:  // COP1X - MIPS IV
			if (m_context.flavor < MIPS3_TYPE_MIPS_IV)
				return false;
			return describe_cop1x(op, desc);

		case 0x1c:  // IDT-specific opcodes: mad/madu/mul on R4640/4650, msub on RC32364
			return describe_idt(op, desc);

		case 0x02:  // J
			desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			desc.targetpc = (desc.pc & 0xf0000000) | (LIMMVAL << 2);
			desc.delayslots = 1;
			return true;

		case 0x03:  // JAL
			desc.regout[0] |= REGFLAG_R(31);
			desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			desc.targetpc = (desc.pc & 0xf0000000) | (LIMMVAL << 2);
			desc.delayslots = 1;
			return true;

		case 0x04:  // BEQ
		case 0x05:  // BNE
		case 0x14:  // BEQL
		case 0x15:  // BNEL
			if ((opswitch == 0x04 || opswitch == 0x14) && RSREG == RTREG)
				desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			else
			{
				desc.regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
				desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
			}
			desc.targetpc = desc.pc + 4 + (SIMMVAL << 2);
			desc.delayslots = 1;
			desc.skipslots = (opswitch & 0x10) ? 1 : 0;
			return true;

		case 0x06:  // BLEZ
		case 0x07:  // BGTZ
		case 0x16:  // BLEZL
		case 0x17:  // BGTZL
			if ((opswitch == 0x06 || opswitch == 0x16) && RSREG == 0)
				desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			else
			{
				desc.regin[0] |= REGFLAG_R(RSREG);
				desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
			}
			desc.targetpc = desc.pc + 4 + (SIMMVAL << 2);
			desc.delayslots = 1;
			desc.skipslots = (opswitch & 0x10) ? 1 : 0;
			return true;

		case 0x08:  // ADDI
		case 0x18:  // DADDI
			desc.regin[0] |= REGFLAG_R(RSREG);
			desc.regout[0] |= REGFLAG_R(RTREG);
			desc.flags |= OPFLAG_CAN_CAUSE_EXCEPTION;
			return true;
//.........这里部分代码省略.........
开发者ID:dezi，项目名称:mame-libretro-odroid，代码行数:101，代码来源:mips3fe.c


示例15: rspfe_describe

int rspfe_describe(void *param, opcode_desc *desc, const opcode_desc *prev)
{
	rsp_state *rsp = (rsp_state *)param;
	UINT32 op, opswitch;

	/* fetch the opcode */
	op = desc->opptr.l[0] = memory_decrypted_read_dword(rsp->program, desc->physpc | 0x1000);

	/* all instructions are 4 bytes and default to a single cycle each */
	desc->length = 4;
	desc->cycles = 1;

	/* parse the instruction */
	opswitch = op >> 26;
	switch (opswitch)
	{
		case 0x00:	/* SPECIAL */
			return describe_instruction_special(rsp, op, desc);

		case 0x01:	/* REGIMM */
			return describe_instruction_regimm(rsp, op, desc);

		case 0x10:	/* COP0 */
			return describe_instruction_cop0(rsp, op, desc);

		case 0x12:	/* COP2 */
			return describe_instruction_cop2(rsp, op, desc);

		case 0x02:	/* J */
			desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			desc->targetpc = ((LIMMVAL << 2) & 0x00000fff) | 0x1000;
			desc->delayslots = 1;
			return TRUE;

		case 0x03:	/* JAL */
			desc->regout[0] |= REGFLAG_R(31);
			desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			desc->targetpc = ((LIMMVAL << 2) & 0x00000fff) | 0x1000;
			desc->delayslots = 1;
			return TRUE;

		case 0x04:	/* BEQ */
		case 0x05:	/* BNE */
			if ((opswitch == 0x04 || opswitch == 0x14) && RSREG == RTREG)
				desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			else
			{
				desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
				desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
			}
			desc->targetpc = ((desc->pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
			desc->delayslots = 1;
			desc->skipslots = (opswitch & 0x10) ? 1 : 0;
			return TRUE;

		case 0x06:	/* BLEZ */
		case 0x07:	/* BGTZ */
			if ((opswitch == 0x06 || opswitch == 0x16) && RSREG == 0)
				desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
			else
			{
				desc->regin[0] |= REGFLAG_R(RSREG);
				desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
			}
			desc->targetpc = ((desc->pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
			desc->delayslots = 1;
			desc->skipslots = (opswitch & 0x10) ? 1 : 0;
			return TRUE;

		case 0x08:	/* ADDI */
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->regout[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x09:	/* ADDIU */
		case 0x0a:	/* SLTI */
		case 0x0b:	/* SLTIU */
		case 0x0c:	/* ANDI */
		case 0x0d:	/* ORI */
		case 0x0e:	/* XORI */
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->regout[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x0f:	/* LUI */
			desc->regout[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x20:	/* LB */
		case 0x21:	/* LH */
		case 0x23:	/* LW */
		case 0x24:	/* LBU */
		case 0x25:	/* LHU */
		case 0x27:	/* LWU */
			desc->regin[0] |= REGFLAG_R(RSREG);
			desc->regout[0] |= REGFLAG_R(RTREG);
			desc->flags |= OPFLAG_READS_MEMORY;
			return TRUE;

		case 0x28:	/* SB */
//.........这里部分代码省略.........
开发者ID:AltimorTASDK，项目名称:shmupmametgm，代码行数:101，代码来源:rspfe.c


示例16: describe_instruction_cop0

static int describe_instruction_cop0(mips3_state *mipsaa, UINT32 op, opcode_desc *desc)
{
	/* any COP0 instruction can potentially cause an exception */
	desc->flags |= OPFLAG_CAN_CAUSE_EXCEPTION;

	switch (RSREG)
	{
		case 0x00:	/* MFCz */
		case 0x01:	/* DMFCz */
			if (RDREG == COP0_Count)
				desc->cycles += MIPS3_COUNT_READ_CYCLES;
			if (RDREG == COP0_Cause)
				desc->cycles += MIPS3_CAUSE_READ_CYCLES;
			desc->regout[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x02:	/* CFCz */
			desc->regout[0] |= REGFLAG_R(RTREG);
			return TRUE;

		case 0x04:	/* MTCz */
		case 0x05:	/* DMTCz */
		case 0x06:	/* CTCz */
			desc->regin[0] |= REGFLAG_R(RTREG);
			if (RSREG == 0x04 || RSREG == 0x05)
			{
				if (RDREG == COP0_Cause)
					desc->flags |= OPFLAG_CAN_TRIGGER_SW_INT;
				if (RDREG == COP0_Status)
					desc->flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT | OPFLAG_CAN_CHANGE_MODES | OPFLAG_END_SEQUENCE;
			}
			return TRUE;

		case 0x08:	/* BC */
			switch (RTREG)
			{
				case 0x00:	/* BCzF */
				case 0x01:	/* BCzT */
					desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
					desc->targetpc = desc->pc + 4 + (SIMMVAL << 2);
					desc->delayslots = 1;
					return TRUE;
			}
			return FALSE;

		case 0x10:	case 0x11:	case 0x12:	case 0x13:	case 0x14:	case 0x15:	case 0x16:	case 0x17:
		case 0x18:	case 0x19:	case 0x1a:	case 0x1b:	case 0x1c:	case 0x1d:	case 0x1e:	case 0x1f:	/* COP */
			switch (op & 0x01ffffff)
			{
				case 0x01:	/* TLBR */
				case 0x08:	/* TLBP */
				case 0x20:	/* WAIT */
					return TRUE;

				case 0x02:	/* TLBWI */
				case 0x06:	/* TLBWR */
					desc->flags |= OPFLAG_MODIFIES_TRANSLATION;
					return TRUE;

				case 0x18:	/* ERET */
					desc->flags |= OPFLAG_CAN_CHANGE_MODES | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
					return TRUE;
			}
			return FALSE;
	}

	return FALSE;
}
开发者ID:DarrenBranford，项目名称:MAME4iOS，代码行数:68，代码来源:mips3fe.c



注：本文中的REGFLAG_R函数示例由纯净天空整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。

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