* all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "priv.h"
#include "fuc/nvc0.fuc.h"

struct nouveau_oclass *
nvc0_pwr_oclass = &(struct nvkm_pwr_impl) {
	.base.handle = NV_SUBDEV(PWR, 0xc0),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = _nouveau_pwr_ctor,
		.dtor = _nouveau_pwr_dtor,
		.init = _nouveau_pwr_init,
		.fini = _nouveau_pwr_fini,
	},
	.code.data = nvc0_pwr_code,
	.code.size = sizeof(nvc0_pwr_code),
	.data.data = nvc0_pwr_data,
	.data.size = sizeof(nvc0_pwr_data),
}.base;

 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "nv50.h"

struct nouveau_oclass *
nva3_fb_oclass = &(struct nv50_fb_impl) {
	.base.base.handle = NV_SUBDEV(FB, 0xa3),
	.base.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv50_fb_ctor,
		.dtor = nv50_fb_dtor,
		.init = nv50_fb_init,
		.fini = _nouveau_fb_fini,
	},
	.base.memtype = nv50_fb_memtype_valid,
	.base.ram = &nva3_ram_oclass,
	.trap = 0x000d0fff,
}.base.base;

		  .fini = _nouveau_i2c_port_fini,
	  },
	},
	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
	  .ofuncs = &(struct nouveau_ofuncs) {
		  .ctor = nv94_aux_port_ctor,
		  .dtor = _nouveau_i2c_port_dtor,
		  .init = _nouveau_i2c_port_init,
		  .fini = _nouveau_i2c_port_fini,
	  },
	},
	{}
};

struct nouveau_oclass *
nv94_i2c_oclass = &(struct nouveau_i2c_impl) {
	.base.handle = NV_SUBDEV(I2C, 0x94),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = _nouveau_i2c_ctor,
		.dtor = _nouveau_i2c_dtor,
		.init = _nouveau_i2c_init,
		.fini = _nouveau_i2c_fini,
	},
	.sclass = nv94_i2c_sclass,
	.pad_x = &nv04_i2c_pad_oclass,
	.pad_s = &nv94_i2c_pad_oclass,
	.aux = 4,
	.aux_stat = nv94_aux_stat,
	.aux_mask = nv94_aux_mask,
}.base;

static int
nvd0_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	      struct nouveau_oclass *oclass, void *data, u32 size,
	      struct nouveau_object **pobject)
{
	struct nvd0_pwr_priv *priv;
	int ret;

	ret = nouveau_pwr_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.code.data = nvd0_pwr_code;
	priv->base.code.size = sizeof(nvd0_pwr_code);
	priv->base.data.data = nvd0_pwr_data;
	priv->base.data.size = sizeof(nvd0_pwr_data);
	return 0;
}

struct nouveau_oclass
nvd0_pwr_oclass = {
	.handle = NV_SUBDEV(PWR, 0xd0),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nvd0_pwr_ctor,
		.dtor = _nouveau_pwr_dtor,
		.init = _nouveau_pwr_init,
		.fini = _nouveau_pwr_fini,
	},
};

 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "priv.h"
#include "fuc/gt215.fuc3.h"

static int
gt215_pmu_init(struct nvkm_object *object)
{
	struct nvkm_pmu *pmu = (void *)object;
	nv_mask(pmu, 0x022210, 0x00000001, 0x00000000);
	nv_mask(pmu, 0x022210, 0x00000001, 0x00000001);
	return nvkm_pmu_init(pmu);
}

struct nvkm_oclass *
gt215_pmu_oclass = &(struct nvkm_pmu_impl) {
	.base.handle = NV_SUBDEV(PMU, 0xa3),
	.base.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = _nvkm_pmu_ctor,
		.dtor = _nvkm_pmu_dtor,
		.init = gt215_pmu_init,
		.fini = _nvkm_pmu_fini,
	},
	.code.data = gt215_pmu_code,
	.code.size = sizeof(gt215_pmu_code),
	.data.data = gt215_pmu_data,
	.data.size = sizeof(gt215_pmu_data),
}.base;

 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "nv04.h"

struct nouveau_oclass *
nv1a_devinit_oclass = &(struct nouveau_devinit_impl) {
	.base.handle = NV_SUBDEV(DEVINIT, 0x1a),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv04_devinit_ctor,
		.dtor = nv04_devinit_dtor,
		.init = nv04_devinit_init,
		.fini = nv04_devinit_fini,
	},
	.pll_set = nv04_devinit_pll_set,
	.post = nvbios_init,
}.base;

	return 0;
}

static int
nv41_vmmgr_init(struct nouveau_object *object)
{
	struct nv04_vmmgr_priv *priv = (void *)object;
	struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0];
	int ret;

	ret = nouveau_vmmgr_init(&priv->base);
	if (ret)
		return ret;

	nv_wr32(priv, 0x100800, dma->addr | 0x00000002);
	nv_mask(priv, 0x10008c, 0x00000100, 0x00000100);
	nv_wr32(priv, 0x100820, 0x00000000);
	return 0;
}

struct nouveau_oclass
nv41_vmmgr_oclass = {
	.handle = NV_SUBDEV(VM, 0x41),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv41_vmmgr_ctor,
		.dtor = nv04_vmmgr_dtor,
		.init = nv41_vmmgr_init,
		.fini = _nouveau_vmmgr_fini,
	},
};

	     struct nouveau_object **pobject)
{
	struct nv20_fb_priv *priv;
	int ret;

	ret = nouveau_fb_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.memtype_valid = nv04_fb_memtype_valid;
	priv->base.ram.init = nv20_fb_vram_init;
	priv->base.tile.regions = 8;
	priv->base.tile.init = nv20_fb_tile_init;
	priv->base.tile.comp = nv20_fb_tile_comp;
	priv->base.tile.fini = nv20_fb_tile_fini;
	priv->base.tile.prog = nv20_fb_tile_prog;
	return nouveau_fb_preinit(&priv->base);
}

struct nouveau_oclass
nv20_fb_oclass = {
	.handle = NV_SUBDEV(FB, 0x20),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv20_fb_ctor,
		.dtor = _nouveau_fb_dtor,
		.init = _nouveau_fb_init,
		.fini = _nouveau_fb_fini,
	},
};

	},
	{}
};

static int
nv50_i2c_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	      struct nouveau_oclass *oclass, void *data, u32 size,
	      struct nouveau_object **pobject)
{
	struct nv50_i2c_priv *priv;
	int ret;

	ret = nouveau_i2c_create(parent, engine, oclass, nv50_i2c_sclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	return 0;
}

struct nouveau_oclass
nv50_i2c_oclass = {
	.handle = NV_SUBDEV(I2C, 0x50),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv50_i2c_ctor,
		.dtor = _nouveau_i2c_dtor,
		.init = _nouveau_i2c_init,
		.fini = _nouveau_i2c_fini,
	},
};

	tile->limit = 0;
	tile->pitch = 0;
	tile->zcomp = 0;
}

void
nv10_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
{
	nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
	nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
	nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
	nv_rd32(pfb, 0x100240 + (i * 0x10));
}

struct nvkm_oclass *
nv10_fb_oclass = &(struct nv04_fb_impl) {
	.base.base.handle = NV_SUBDEV(FB, 0x10),
	.base.base.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = nv04_fb_ctor,
		.dtor = _nvkm_fb_dtor,
		.init = _nvkm_fb_init,
		.fini = _nvkm_fb_fini,
	},
	.base.memtype = nv04_fb_memtype_valid,
	.base.ram = &nv10_ram_oclass,
	.tile.regions = 8,
	.tile.init = nv10_fb_tile_init,
	.tile.fini = nv10_fb_tile_fini,
	.tile.prog = nv10_fb_tile_prog,
}.base.base;

		return ret;

	/* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */
	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00800, 0,
				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
	if (ret)
		return ret;

	/* 0x18800-0x18a00: reserve for RAMRO */
	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0,
				&priv->ramro);
	if (ret)
		return ret;

	return 0;
}

struct nouveau_oclass *
nv04_instmem_oclass = &(struct nouveau_instmem_impl) {
	.base.handle = NV_SUBDEV(INSTMEM, 0x04),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv04_instmem_ctor,
		.dtor = nv04_instmem_dtor,
		.init = _nouveau_instmem_init,
		.fini = _nouveau_instmem_fini,
		.rd32 = nv04_instmem_rd32,
		.wr32 = nv04_instmem_wr32,
	},
	.instobj = &nv04_instobj_oclass.base,
}.base;

		struct nouveau_object **pobject)
{
	struct nva3_therm_priv *priv;
	int ret;

	ret = nouveau_therm_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl;
	priv->base.base.pwm_get = nv50_fan_pwm_get;
	priv->base.base.pwm_set = nv50_fan_pwm_set;
	priv->base.base.pwm_clock = nv50_fan_pwm_clock;
	priv->base.base.temp_get = nv84_temp_get;
	priv->base.base.fan_sense = nva3_therm_fan_sense;
	priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
	return nouveau_therm_preinit(&priv->base.base);
}

struct nouveau_oclass
nva3_therm_oclass = {
	.handle = NV_SUBDEV(THERM, 0xa3),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nva3_therm_ctor,
		.dtor = _nouveau_therm_dtor,
		.init = nva3_therm_init,
		.fini = nv84_therm_fini,
	},
};

	nvkm_therm_sensor_set_threshold_state(&priv->base.base,
					      NVKM_THERM_THRS_DOWNCLOCK,
					      NVKM_THERM_THRS_LOWER);

	return nvkm_therm_preinit(&priv->base.base);
}

int
g84_therm_fini(struct nvkm_object *object, bool suspend)
{
	/* Disable PTherm IRQs */
	nv_wr32(object, 0x20000, 0x00000000);

	/* ACK all PTherm IRQs */
	nv_wr32(object, 0x20100, 0xffffffff);
	nv_wr32(object, 0x1100, 0x10000); /* PBUS */

	return _nvkm_therm_fini(object, suspend);
}

struct nvkm_oclass
g84_therm_oclass = {
	.handle = NV_SUBDEV(THERM, 0x84),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = g84_therm_ctor,
		.dtor = _nvkm_therm_dtor,
		.init = g84_therm_init,
		.fini = g84_therm_fini,
	},
};

static int
nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		struct nouveau_oclass *oclass, void *data, u32 size,
		struct nouveau_object **pobject)
{
	struct nv04_clock_priv *priv;
	int ret;

	ret = nouveau_clock_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.pll_set = nv04_clock_pll_set;
	priv->base.pll_calc = nv04_clock_pll_calc;
	priv->base.pll_prog = nv04_clock_pll_prog;
	return 0;
}

struct nouveau_oclass
nv04_clock_oclass = {
	.handle = NV_SUBDEV(CLOCK, 0x04),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv04_clock_ctor,
		.dtor = _nouveau_clock_dtor,
		.init = _nouveau_clock_init,
		.fini = _nouveau_clock_fini,
	},
};

{
	u32 tiles = DIV_ROUND_UP(size, 0x40);
	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
	if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
		if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */
		else              tile->zcomp = 0x00200000; /* Z24S8 */
		tile->zcomp |= tile->tag->offset;
#ifdef __BIG_ENDIAN
		tile->zcomp |= 0x01000000;
#endif
	}
}

struct nvkm_oclass *
nv25_fb_oclass = &(struct nv04_fb_impl) {
	.base.base.handle = NV_SUBDEV(FB, 0x25),
	.base.base.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = nv04_fb_ctor,
		.dtor = _nvkm_fb_dtor,
		.init = _nvkm_fb_init,
		.fini = _nvkm_fb_fini,
	},
	.base.memtype = nv04_fb_memtype_valid,
	.base.ram = &nv20_ram_oclass,
	.tile.regions = 8,
	.tile.init = nv20_fb_tile_init,
	.tile.comp = nv25_fb_tile_comp,
	.tile.fini = nv20_fb_tile_fini,
	.tile.prog = nv20_fb_tile_prog,
}.base.base;

	nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001);
	nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000);

	nv_mask(ppwr, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
	msleep(50);

	nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000000);
	nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001);
	nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000);

	nv_mask(ppwr, 0x000200, 0x08000000, 0x00000000);
	nv_mask(ppwr, 0x000200, 0x00001000, 0x00001000);
	nv_rd32(ppwr, 0x000200);
}

struct nouveau_oclass *
gk104_pwr_oclass = &(struct nvkm_pwr_impl) {
	.base.handle = NV_SUBDEV(PWR, 0xe4),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = _nouveau_pwr_ctor,
		.dtor = _nouveau_pwr_dtor,
		.init = _nouveau_pwr_init,
		.fini = _nouveau_pwr_fini,
	},
	.code.data = gk104_pwr_code,
	.code.size = sizeof(gk104_pwr_code),
	.data.data = gk104_pwr_data,
	.data.size = sizeof(gk104_pwr_data),
	.pgob = gk104_pwr_pgob,
}.base;

	{},
};

static void
nv50_mc_msi_rearm(struct nouveau_mc *pmc)
{
	struct nouveau_device *device = nv_device(pmc);
	pci_write_config_byte(device->pdev, 0x68, 0xff);
}

int
nv50_mc_init(struct nouveau_object *object)
{
	struct nv04_mc_priv *priv = (void *)object;
	nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */
	return nouveau_mc_init(&priv->base);
}

struct nouveau_oclass *
nv50_mc_oclass = &(struct nouveau_mc_oclass) {
	.base.handle = NV_SUBDEV(MC, 0x50),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv04_mc_ctor,
		.dtor = _nouveau_mc_dtor,
		.init = nv50_mc_init,
		.fini = _nouveau_mc_fini,
	},
	.intr = nv50_mc_intr,
	.msi_rearm = nv50_mc_msi_rearm,
}.base;

 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "nvc0.h"

struct nouveau_oclass *
gm107_fb_oclass = &(struct nouveau_fb_impl) {
	.base.handle = NV_SUBDEV(FB, 0x07),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nvc0_fb_ctor,
		.dtor = nvc0_fb_dtor,
		.init = nvc0_fb_init,
		.fini = _nouveau_fb_fini,
	},
	.memtype = nvc0_fb_memtype_valid,
	.ram = &gm107_ram_oclass,
}.base;

};

static int
nvc0_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	     struct nouveau_oclass *oclass, void *data, u32 size,
	     struct nouveau_object **pobject)
{
	struct nvc0_mc_priv *priv;
	int ret;

	ret = nouveau_mc_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_subdev(priv)->intr = nouveau_mc_intr;
	priv->base.intr_map = nvc0_mc_intr;
	return 0;
}

struct nouveau_oclass
nvc0_mc_oclass = {
	.handle = NV_SUBDEV(MC, 0xc0),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nvc0_mc_ctor,
		.dtor = _nouveau_mc_dtor,
		.init = nv50_mc_init,
		.fini = _nouveau_mc_fini,
	},
};

	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_subdev(priv)->intr = nouveau_mc_intr;
	priv->base.intr_map = nv04_mc_intr;
	return 0;
}

int
nv04_mc_init(struct nouveau_object *object)
{
	struct nv04_mc_priv *priv = (void *)object;

	nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */
	nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */

	return nouveau_mc_init(&priv->base);
}

struct nouveau_oclass
nv04_mc_oclass = {
	.handle = NV_SUBDEV(MC, 0x04),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv04_mc_ctor,
		.dtor = _nouveau_mc_dtor,
		.init = nv04_mc_init,
		.fini = _nouveau_mc_fini,
	},
};