本文整理汇总了C++中GT_READ函数的典型用法代码示例。如果您正苦于以下问题：C++ GT_READ函数的具体用法？C++ GT_READ怎么用？C++ GT_READ使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了GT_READ函数的20个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: gt64240_p0int_irq
static void gt64240_p0int_irq(int irq, void *dev_id, struct pt_regs *regs)
{
uint32_t irq_src, irq_src_mask;
int handled;
/* get the low interrupt cause register */
GT_READ(LOW_INTERRUPT_CAUSE_REGISTER, &irq_src);
/* get the mask register for this pin */
GT_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, &irq_src_mask);
/* mask off only the interrupts we're interested in */
irq_src = irq_src & irq_src_mask;
handled = 0;
/* Check for timer interrupt */
if (irq_src & 0x00000100) {
handled = 1;
irq_src &= ~0x00000100;
/* Clear any pending cause bits */
GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
/* handle the timer call */
do_timer(regs);
}
if (irq_src) {
printk(KERN_INFO
"UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
irq_src);
}
}
开发者ID:Picture-Elements，项目名称:linux-2.4-peijse，代码行数:34，代码来源:gt-irq.c
示例2: gt64120_irq
static irqreturn_t gt64120_irq(int irq, void *dev_id)
{
unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;
int handled = 0;
irq_src = GT_READ(GT_INTRCAUSE_OFS);
irq_src_mask = GT_READ(GT_INTRMASK_OFS);
int_high_src = GT_READ(GT_HINTRCAUSE_OFS);
int_high_src_mask = GT_READ(GT_HINTRMASK_OFS);
irq_src = irq_src & irq_src_mask;
int_high_src = int_high_src & int_high_src_mask;
if (irq_src & 0x00000800) { /* Check for timer interrupt */
handled = 1;
irq_src &= ~0x00000800;
do_timer(1);
#ifndef CONFIG_SMP
update_process_times(user_mode(get_irq_regs()));
#endif
}
GT_WRITE(GT_INTRCAUSE_OFS, 0);
GT_WRITE(GT_HINTRCAUSE_OFS, 0);
return IRQ_HANDLED;
}
开发者ID:3sOx，项目名称:asuswrt-merlin，代码行数:26，代码来源:time.c
示例3: corehi_irqdispatch
void corehi_irqdispatch(struct pt_regs *regs)
{
unsigned int intrcause,datalo,datahi;
unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;
printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
/* Read all the registers and then print them as there is a
problem with interspersed printk's upsetting the Bonito controller.
Do it for the others too.
*/
switch(mips_revision_corid) {
case MIPS_REVISION_CORID_CORE_MSC:
case MIPS_REVISION_CORID_CORE_FPGA2:
case MIPS_REVISION_CORID_CORE_FPGA3:
case MIPS_REVISION_CORID_CORE_24K:
case MIPS_REVISION_CORID_CORE_EMUL_MSC:
ll_msc_irq(regs);
break;
case MIPS_REVISION_CORID_QED_RM5261:
case MIPS_REVISION_CORID_CORE_LV:
case MIPS_REVISION_CORID_CORE_FPGA:
case MIPS_REVISION_CORID_CORE_FPGAR2:
intrcause = GT_READ(GT_INTRCAUSE_OFS);
datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
printk("GT_INTRCAUSE = %08x\n", intrcause);
printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
break;
case MIPS_REVISION_CORID_BONITO64:
case MIPS_REVISION_CORID_CORE_20K:
case MIPS_REVISION_CORID_CORE_EMUL_BON:
pcibadaddr = BONITO_PCIBADADDR;
pcimstat = BONITO_PCIMSTAT;
intisr = BONITO_INTISR;
inten = BONITO_INTEN;
intpol = BONITO_INTPOL;
intedge = BONITO_INTEDGE;
intsteer = BONITO_INTSTEER;
pcicmd = BONITO_PCICMD;
printk("BONITO_INTISR = %08x\n", intisr);
printk("BONITO_INTEN = %08x\n", inten);
printk("BONITO_INTPOL = %08x\n", intpol);
printk("BONITO_INTEDGE = %08x\n", intedge);
printk("BONITO_INTSTEER = %08x\n", intsteer);
printk("BONITO_PCICMD = %08x\n", pcicmd);
printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
break;
}
/* We die here*/
die("CoreHi interrupt", regs);
}
开发者ID:Broadcom，项目名称:stblinux-2.6.18，代码行数:57，代码来源:malta_int.c
示例4: gt64xxx_pci0_pcibios_config_access
static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
{
unsigned char busnum = bus->number;
u32 intr;
if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
return -1; /* */
/* */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
/* */
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) |
(devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
GT_PCI0_CFGADDR_CONFIGEN_BIT);
if (access_type == PCI_ACCESS_WRITE) {
if (busnum == 0 && PCI_SLOT(devfn) == 0) {
/*
*/
GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
} else
__GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
} else {
if (busnum == 0 && PCI_SLOT(devfn) == 0) {
/*
*/
*data = GT_READ(GT_PCI0_CFGDATA_OFS);
} else
*data = __GT_READ(GT_PCI0_CFGDATA_OFS);
}
/* */
intr = GT_READ(GT_INTRCAUSE_OFS);
if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
/* */
/* */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
return -1;
}
return 0;
}
开发者ID:romanbb，项目名称:android_kernel_lge_d851，代码行数:55，代码来源:ops-gt64xxx_pci0.c
示例5: gt64xxx_pci0_pcibios_config_access
static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
{
unsigned char busnum = bus->number;
u32 intr;
if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
return -1; /* Because of a bug in the galileo (for slot 31). */
/* Clear cause register bits */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
/* Setup address */
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) |
(devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
GT_PCI0_CFGADDR_CONFIGEN_BIT);
if (access_type == PCI_ACCESS_WRITE) {
if (busnum == 0 && PCI_SLOT(devfn) == 0) {
/*
* The Galileo system controller is acting
* differently than other devices.
*/
GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
} else
__GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
} else {
if (busnum == 0 && PCI_SLOT(devfn) == 0) {
/*
* The Galileo system controller is acting
* differently than other devices.
*/
*data = GT_READ(GT_PCI0_CFGDATA_OFS);
} else
*data = __GT_READ(GT_PCI0_CFGDATA_OFS);
}
/* Check for master or target abort */
intr = GT_READ(GT_INTRCAUSE_OFS);
if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
/* Error occurred */
/* Clear bits */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
return -1;
}
return 0;
}
开发者ID:Medvedroid，项目名称:OT_903D-kernel-2.6.35.7，代码行数:55，代码来源:ops-gt64xxx_pci0.c
示例6: corehi_irqdispatch
static void corehi_irqdispatch(void)
{
unsigned int intedge, intsteer, pcicmd, pcibadaddr;
unsigned int pcimstat, intisr, inten, intpol;
unsigned int intrcause, datalo, datahi;
struct pt_regs *regs = get_irq_regs();
printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
"Cause : %08lx\nbadVaddr : %08lx\n",
regs->cp0_epc, regs->cp0_status,
regs->cp0_cause, regs->cp0_badvaddr);
/* Read all the registers and then print them as there is a
problem with interspersed printk's upsetting the Bonito controller.
Do it for the others too.
*/
switch (mips_revision_sconid) {
case MIPS_REVISION_SCON_SOCIT:
case MIPS_REVISION_SCON_ROCIT:
case MIPS_REVISION_SCON_SOCITSC:
case MIPS_REVISION_SCON_SOCITSCP:
ll_msc_irq();
break;
case MIPS_REVISION_SCON_GT64120:
intrcause = GT_READ(GT_INTRCAUSE_OFS);
datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
datahi, datalo);
break;
case MIPS_REVISION_SCON_BONITO:
pcibadaddr = BONITO_PCIBADADDR;
pcimstat = BONITO_PCIMSTAT;
intisr = BONITO_INTISR;
inten = BONITO_INTEN;
intpol = BONITO_INTPOL;
intedge = BONITO_INTEDGE;
intsteer = BONITO_INTSTEER;
pcicmd = BONITO_PCICMD;
printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
break;
}
die("CoreHi interrupt", regs);
}
开发者ID:007kumarraja，项目名称:rockchip-rk3188-mk908，代码行数:55，代码来源:malta-int.c
示例7: gt64120_pci_init
static int __init gt64120_pci_init(void)
{
u32 tmp;
tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
tmp = GT_READ(GT_PCI0_BARE_OFS);
/* reset the whole PCI I/O space range */
ioport_resource.start = GT_PCI_IO_BASE;
ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
register_pci_controller(&hose_0);
return 0;
}
开发者ID:274914765，项目名称:C，代码行数:14，代码来源:pci.c
示例8: mask_ack_gt641xx_irq
static void mask_ack_gt641xx_irq(struct irq_data *d)
{
unsigned long flags;
u32 cause, mask;
raw_spin_lock_irqsave(>641xx_irq_lock, flags);
mask = GT_READ(GT_INTRMASK_OFS);
mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
GT_WRITE(GT_INTRMASK_OFS, mask);
cause = GT_READ(GT_INTRCAUSE_OFS);
cause &= ~GT641XX_IRQ_TO_BIT(d->irq);
GT_WRITE(GT_INTRCAUSE_OFS, cause);
raw_spin_unlock_irqrestore(>641xx_irq_lock, flags);
}
开发者ID:AdaLovelance，项目名称:lxcGrsecKernels，代码行数:15，代码来源:irq-gt641xx.c
示例9: gt641xx_timer0_set_mode
static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
u32 ctrl;
raw_spin_lock(>641xx_timer_lock);
ctrl = GT_READ(GT_TC_CONTROL_OFS);
ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;
break;
case CLOCK_EVT_MODE_ONESHOT:
ctrl |= GT_TC_CONTROL_ENTC0_MSK;
break;
default:
break;
}
GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
raw_spin_unlock(>641xx_timer_lock);
}
开发者ID:12019，项目名称:linux-2.6.34-ts471x，代码行数:25，代码来源:cevt-gt641xx.c
示例10: mips_pcibios_iack
static inline int mips_pcibios_iack(void)
{
int irq;
switch (mips_revision_sconid) {
case MIPS_REVISION_SCON_SOCIT:
case MIPS_REVISION_SCON_ROCIT:
case MIPS_REVISION_SCON_SOCITSC:
case MIPS_REVISION_SCON_SOCITSCP:
MSC_READ(MSC01_PCI_IACK, irq);
irq &= 0xff;
break;
case MIPS_REVISION_SCON_GT64120:
irq = GT_READ(GT_PCI0_IACK_OFS);
irq &= 0xff;
break;
case MIPS_REVISION_SCON_BONITO:
BONITO_PCIMAP_CFG = 0x20000;
(void) BONITO_PCIMAP_CFG;
iob();
irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
iob();
irq &= 0xff;
BONITO_PCIMAP_CFG = 0;
break;
default:
printk(KERN_WARNING "Unknown system controller.\n");
return -1;
}
return irq;
}
开发者ID:Blackburn29，项目名称:PsycoKernel，代码行数:34，代码来源:malta-int.c
示例11: galileo_irq
static inline void galileo_irq(void)
{
unsigned int mask, pending, devfn;
mask = GT_READ(GT_INTRMASK_OFS);
pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
if (pending & GT_INTR_T0EXP_MSK) {
GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
do_IRQ(COBALT_GALILEO_IRQ);
} else if (pending & GT_INTR_RETRYCTR0_MSK) {
devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
printk(KERN_WARNING
"Galileo: PCI retry count exceeded (%02x.%u)\n",
PCI_SLOT(devfn), PCI_FUNC(devfn));
} else {
开发者ID:420GrayFox，项目名称:dsl-n55u-bender，代码行数:17，代码来源:irq.c
示例12: gt641xx_timer0_state
int gt641xx_timer0_state(void)
{
if (GT_READ(GT_TC0_OFS))
return 0;
GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);
return 1;
}
开发者ID:12019，项目名称:linux-2.6.34-ts471x，代码行数:10，代码来源:cevt-gt641xx.c
示例13: corehi_irqdispatch
void corehi_irqdispatch(struct pt_regs *regs)
{
unsigned int data,datahi;
/* Mask out corehi interrupt. */
clear_c0_status(IE_IRQ3);
printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
switch(mips_revision_corid) {
case MIPS_REVISION_CORID_CORE_MSC:
break;
case MIPS_REVISION_CORID_QED_RM5261:
case MIPS_REVISION_CORID_CORE_LV:
case MIPS_REVISION_CORID_CORE_FPGA:
data = GT_READ(GT_INTRCAUSE_OFS);
printk("GT_INTRCAUSE = %08x\n", data);
data = GT_READ(0x70);
datahi = GT_READ(0x78);
printk("GT_CPU_ERR_ADDR = %0x2%08x\n", datahi,data);
break;
case MIPS_REVISION_CORID_BONITO64:
case MIPS_REVISION_CORID_CORE_20K:
data = BONITO_INTISR;
printk("BONITO_INTISR = %08x\n", data);
data = BONITO_INTEN;
printk("BONITO_INTEN = %08x\n", data);
data = BONITO_INTPOL;
printk("BONITO_INTPOL = %08x\n", data);
data = BONITO_INTEDGE;
printk("BONITO_INTEDGE = %08x\n", data);
data = BONITO_INTSTEER;
printk("BONITO_INTSTEER = %08x\n", data);
data = BONITO_PCICMD;
printk("BONITO_PCICMD = %08x\n", data);
break;
}
/* We die here*/
die("CoreHi interrupt", regs);
}
开发者ID:iPodLinux，项目名称:linux-2.4.24-ipod，代码行数:42，代码来源:malta_int.c
示例14: unmask_gt641xx_irq
static void unmask_gt641xx_irq(struct irq_data *d)
{
unsigned long flags;
u32 mask;
raw_spin_lock_irqsave(>641xx_irq_lock, flags);
mask = GT_READ(GT_INTRMASK_OFS);
mask |= GT641XX_IRQ_TO_BIT(d->irq);
GT_WRITE(GT_INTRMASK_OFS, mask);
raw_spin_unlock_irqrestore(>641xx_irq_lock, flags);
}
开发者ID:AdaLovelance，项目名称:lxcGrsecKernels，代码行数:11，代码来源:irq-gt641xx.c
示例15: gt64120_irq
static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;
int handled = 0;
irq_src = GT_READ(GT_INTRCAUSE_OFS);
irq_src_mask = GT_READ(GT_INTRMASK_OFS);
int_high_src = GT_READ(GT_HINTRCAUSE_OFS);
int_high_src_mask = GT_READ(GT_HINTRMASK_OFS);
irq_src = irq_src & irq_src_mask;
int_high_src = int_high_src & int_high_src_mask;
if (irq_src & 0x00000800) { /* Check for timer interrupt */
handled = 1;
irq_src &= ~0x00000800;
do_timer(regs);
}
GT_WRITE(GT_INTRCAUSE_OFS, 0);
GT_WRITE(GT_HINTRCAUSE_OFS, 0);
}
开发者ID:12019，项目名称:hg556a_source，代码行数:21，代码来源:time.c
示例16: malta_hw0_irqdispatch
void malta_hw0_irqdispatch(struct pt_regs *regs)
{
int irq;
/*
* Determine highest priority pending interrupt by performing a PCI
* Interrupt Acknowledge cycle.
*/
GT_READ(GT_PCI0_IACK_OFS, irq);
irq &= 0xFF;
do_IRQ(irq, regs);
}
开发者ID:nhanh0，项目名称:hah，代码行数:13，代码来源:malta_int.c
示例17: gt641xx_timer0_set_periodic
static int gt641xx_timer0_set_periodic(struct clock_event_device *evt)
{
u32 ctrl;
raw_spin_lock(>641xx_timer_lock);
ctrl = GT_READ(GT_TC_CONTROL_OFS);
ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;
GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
raw_spin_unlock(>641xx_timer_lock);
return 0;
}
开发者ID:0-T-0，项目名称:ps4-linux，代码行数:13，代码来源:cevt-gt641xx.c
示例18: mips_pcibios_iack
static inline int mips_pcibios_iack(void)
{
int irq;
u32 dummy;
/*
* Determine highest priority pending interrupt by performing
* a PCI Interrupt Acknowledge cycle.
*/
switch(mips_revision_corid) {
case MIPS_REVISION_CORID_CORE_MSC:
case MIPS_REVISION_CORID_CORE_FPGA2:
case MIPS_REVISION_CORID_CORE_FPGA3:
case MIPS_REVISION_CORID_CORE_24K:
case MIPS_REVISION_CORID_CORE_EMUL_MSC:
MSC_READ(MSC01_PCI_IACK, irq);
irq &= 0xff;
break;
case MIPS_REVISION_CORID_QED_RM5261:
case MIPS_REVISION_CORID_CORE_LV:
case MIPS_REVISION_CORID_CORE_FPGA:
case MIPS_REVISION_CORID_CORE_FPGAR2:
irq = GT_READ(GT_PCI0_IACK_OFS);
irq &= 0xff;
break;
case MIPS_REVISION_CORID_BONITO64:
case MIPS_REVISION_CORID_CORE_20K:
case MIPS_REVISION_CORID_CORE_EMUL_BON:
/* The following will generate a PCI IACK cycle on the
* Bonito controller. It's a little bit kludgy, but it
* was the easiest way to implement it in hardware at
* the given time.
*/
BONITO_PCIMAP_CFG = 0x20000;
/* Flush Bonito register block */
dummy = BONITO_PCIMAP_CFG;
iob(); /* sync */
irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
iob(); /* sync */
irq &= 0xff;
BONITO_PCIMAP_CFG = 0;
break;
default:
printk("Unknown Core card, don't know the system controller.\n");
return -1;
}
return irq;
}
开发者ID:qwerty1023，项目名称:wive-rtnl-firmware，代码行数:50，代码来源:malta_int.c
示例19: plat_timer_setup
void __init plat_timer_setup(struct irqaction *irq)
{
/* Load timer value for HZ (TCLK is 50MHz) */
GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
/* Enable timer */
GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
/* Register interrupt */
setup_irq(COBALT_GALILEO_IRQ, irq);
/* Enable interrupt */
GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
}
开发者ID:420GrayFox，项目名称:dsl-n55u-bender，代码行数:14，代码来源:setup.c
示例20: gt641xx_irq_dispatch
void gt641xx_irq_dispatch(void)
{
u32 cause, mask;
int i;
cause = GT_READ(GT_INTRCAUSE_OFS);
mask = GT_READ(GT_INTRMASK_OFS);
cause &= mask;
/*
* bit0 : logical or of all the interrupt bits.
* bit30: logical or of bits[29:26,20:1].
* bit31: logical or of bits[25:1].
*/
for (i = 1; i < 30; i++) {
if (cause & (1U << i)) {
do_IRQ(GT641XX_IRQ_BASE + i);
return;
}
}
atomic_inc_unchecked(&irq_err_count);
}
开发者ID:AdaLovelance，项目名称:lxcGrsecKernels，代码行数:23，代码来源:irq-gt641xx.c
注：本文中的GT_READ函数示例由纯净天空整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。 |
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